MC68030CRC25C Freescale Semiconductor, MC68030CRC25C Datasheet - Page 127
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MC68030CRC25C
Manufacturer Part Number
MC68030CRC25C
Description
IC MPU 32BIT ENHANCED 128-PGA
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68030FE20C.pdf
(599 pages)
Specifications of MC68030CRC25C
Processor Type
M680x0 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
128-PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
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5
5-2
5.1 SIGNAL INDEX
found in M68030EC/D, MC68030 E/ectrical Specifications..
T h e i n p u t a n d o u t p u t s i g n a l s f o r t h e M C 6 8 0 3 0 are l i s t e d in T a b l e 5-1. B o t h
t h e n a m e s a n d m n e m o n i c s
f o r t h e s i g n a l a n d t h e r e f e r e n c e in t h a t p a r a g r a p h t o a d e s c r i p t i o n o f t h e
Guaranteed timing specifications for the signals listed in Table 5-1 can be
For m o r e d e t a i l o n each s i g n a l , r e f e r t o t h e p a r a g r a p h in t h i s s e c t i o n n a m e d
r e l a t e d o p e r a t i o n s .
Function Codes
Address Bus
Data Bus
Size
Operand Cycle Start
External Cycle Start
Read/Write
Read-Modify-Write Cycle
Address Strobe
Data
Data Strobe
t e r m s a r e u s e d i n d e p e n d e n t l y o f t h e v o l t a g e level ( h i g h o r l o w ) t h a t
t h e y r e p r e s e n t .
n e g a t i o n are u s e d t o s p e c i f y f o r c i n g a s i g n a l t o a p a r t i c u l a r state. In
p a r t i c u l a r , a s s e r t i o n a n d
n e g a t i o n a n d n e g a t e i n d i c a t e a s i g n a l t h a t is i n a c t i v e o r false. T h e s e
In t h i s s e c t i o n a n d in t h e r e m a i n d e r o f t h e m a n u a l , a s s e r t i o n a n d
Buffer Enable
Signal Name
Table 5-1. Signal Index (Sheet 1 of 2)
Mnemonic
SIZO/SIZ1 Indicates the number of bytes remaining to be transferred
FC0-FC2
A0-A31
D0-D31
DBEN
MC68030 USER'S MANUAL
RMC
OCS
ECS
R/W
AS
DS
a r e
a s s e r t
32-bit data
for this cycle. These signals, together with A0 and A1, define
the active sections of the data bus.
only during the first bus cycle of an operand transfer.
an external device or has been placed on the data bus by
the MC68030.
each bus cycle.
Identical operation to that of ECS except that OCS is asserted
Provides an indication that a bus cycle is beginning.
Defines the bus transfer as a processor read or write.
Provides an indicator that the current bus cycle is part of an
indivisible read-modify-write operation.
Indicates that a valid address is on the bus.
Indicates that valid data is to be placed on the data bus by
Provides an enable signal for
3-bit function code used to identify the address space of
32-bit address bus.
3er bus cycle.
s h o w n a l o n g w i t h b r i e f s i g n a l d e s c r i p t i o n s .
NOTE
r e f e r to a s i g n a l t h a t is a c t i v e o r t r u e ;
bus
used to transfer 8, 16, 24, or 32 bits of
Function
external data
buffers.
MOTOROLA
data
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