MC68030CRC25C Freescale Semiconductor, MC68030CRC25C Datasheet - Page 9

• Manufacturer Part Number: MC68030CRC25C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Paragraph
MOTOROLA
Number
6.3.1.2
6.3.1.6
6.3.1.3
6.3.1.4
6.3.1.5
6.3.1.7
6.3.1.8
6.3.1.9
6.3.1.10
6.3.1.11
6.3.2
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.10
7.2.7
7.2.8
7.2.9
7.3
7.3.1
7.3.2
7.3.3
7.3.4
Bus
Data Transfer M e c h a n i s m ........................................................
Data Transfer Cycles ...............................................................
Cache Address Register .....................................................
Address Bus .....................................................................
Address Strobe .................................................................
Address, Size, and Data Bus Relationships ..........................
A s y n c h r o n o u s Write Cycle .................................................
Bus Control Signals ..........................................................
Data Bus ..........................................................................
Data Strobe ......................................................................
Data Buffer Enable ............................................................
D y n a m i c Bus Sizing ..........................................................
Cache Filling ....................................................................
Cache Interactions ............................................................
A s y n c h r o n o u s Operation ....................................................
S y n c h r o n o u s Operation w i t h DSACKx .................................
S y n c h r o n o u s Operation w i t h STERM ..................................
A s y n c h r o n o u s Read Cycle .................................................
A s y n c h r o n o u s R e a d - M o d i f y - W r i t e Cycle ..............................
TABLE OF CONTENTS (Continued)
Transfer Signals ...............................................................
M i s a l i g n e d Operands ........................................................
Effects of D y n a m i c Bus Sizing and Operand M i s a l i g n m e n t .... 7-19
MC68030 versus MC68020 D y n a m i c Bus Sizing ....................
S y n c h r o n o u s Read Cycle ...................................................
Bus Cycle T e r m i n a t i o n Signals ...........................................
Clear Entry in Data Cache ...........................................
Clear Entry in Instruction Cache ..................................
Data Burst Enable .......................................................
Clear Data Cache .......................................................
Freeze Data Cache .....................................................
Enable Data Cache .....................................................
Instruction Burst Enable .............................................
Clear Instruction Cache ...............................................
Freeze Instruction Cache .............................................
Enable Instruction Cache .............................................
MC68030 USER'S MANUAL
Bus Operation
Section 7
Title
Number
Page
6-21
7-29
7-31
7-37
7-43
7-48
6-21
6-21
6-22
6-22
6-22
6-22
6-22
6-23
6-23
6-23
7-1
7-3
7-4
7-5
7-5
7-5
7-6
7-6
7-13
7-22
7-24
7-24
7-26
7-27
7-28
7-30
7-4
7-5
vii