MC68030CRC25C Freescale Semiconductor, MC68030CRC25C Datasheet - Page 287
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MC68030CRC25C
Manufacturer Part Number
MC68030CRC25C
Description
IC MPU 32BIT ENHANCED 128-PGA
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68030FE20C.pdf
(599 pages)
Specifications of MC68030CRC25C
Processor Type
M680x0 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
128-PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
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8
8-20
When processing an interrupt exception, the processor first makes an internal
copy of the status register, sets the privilege level to supervisor, suppresses
tracing, and sets the processor interrupt mask level to the level of the interrupt
that cannot supply an interrupt vector, the autovector signal (AVEC) can be
being serviced. The processor attempts to obtain a vector number from the
interrupting device using an interrupt acknowledge bus cycle with the inter-
rupt level number output on pins A1-A3 of the address bus. For a device
asserted, and the MC68030 uses an internally generated autovector, which
is one of vector numbers 25-31, that corresponds to the interrupt level num-
ber. If external logic indicates a bus error during the interrupt acknowledge
cycle, the interrupt is considered spurious, and the processor generates the
spurious interrupt vector number, 24. Refer to 7.4.1 Interrupt Acknowledge
Bus Cycles for complete interrupt bus cycle information.
Figure 8-6. Examples of Interrupt Recognition and Instruction Boundaries
S T A T U S _ _ /
STATUS
N--'~
I P E N ~ - - ~
IPE
CLK
CLK
- - ~
•
EXAMPLE 7: INTERRUPT
EXAMPLE 2: INTEBBUPT EXCEPTION SIGNALED DURING STATO
MC68030 USER'S MANUAL
EXCEPTION SIGNALEO
~ " ~
STAT1
STATO
OURING
STATi
v EXCEPTION PROCESSING
PROCEED TO INTERRUPT
PROCEED TO INTERRUPT
EXCEPTION PROCESSING
MOTOROLA
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