MC68030CRC25C Freescale Semiconductor, MC68030CRC25C Datasheet - Page 272
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MC68030CRC25C
Manufacturer Part Number
MC68030CRC25C
Description
IC MPU 32BIT ENHANCED 128-PGA
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68030FE20C.pdf
(599 pages)
Specifications of MC68030CRC25C
Processor Type
M680x0 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
128-PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
- Current page: 272 of 599
- Download datasheet (23Mb)
8.1.1 Reset E x c e p t i o n
MOTOROLA
Assertion by external hardware of the RESE-I = signal causes a reset exception.
The reset exception has the highest priority of any exception; it provides for
system initialization and recovery from catastrophic failure. When reset is
the following operations:
After the initial instruction prefetches, program execution begins at the ad-
dress in the program counter. The reset exception does not flush the address
translation cache (ATC), nor does it save the value of either the program
counter or the status register.
OPERATION.
recognized, it aborts any processing in progress, and that processing cannot
be recovered. Figure 8-1 is a flowchart of the reset exception, which performs
For details on the requirements for the assertion of RESET, refer to 7.8 RESET
10. Loads the second long word of the reset exception vector into the
3. Sets the processor interrupt priority mask to the highest priority level
4. Initializes the vector base register to zero ($00000000).
6. Invalidates all entries in the instruction and data caches.
7. Clears the enable bit in the translation control register and the enable
8. Generates a vector number to reference the reset exception vector (two
9. Loads the first long word of the reset exception vector into the interrupt
2. Places the processor in the interrupt mode of the supervisor privilege
5. Clears the enable, freeze, and burst enable bits for both on-chip caches
1. Clears both trace bits in the status register to disable tracing.
level by setting the supervisor bit and clearing the master bit in the
status register.
(level 7).
and the write-allocate bit for the data cache in the cache control register.
bits in both transparent translation registers of the MMU.
long words) at offset zero in the supervisor program address space.
stack pointer.
program counter.
MC68030 USER'S MANUAL
8-5
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