MPC8313EVRAFFB Freescale Semiconductor, MPC8313EVRAFFB Datasheet - Page 52

• Manufacturer Part Number: MPC8313EVRAFFB
• Description: IC MPU POWERQUICC II PRO 516PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313EVRAFFB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 333MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 516-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8313E-RDB
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: - 0.3 V to + 1.26 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 16 KB
• I/o Voltage: 2.5 V
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• Program Memory Type: EEPROM/Flash
• For Use With: MPC8313E-RDB - BOARD PROCESSOR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

JTAG
Figure 41
Figure 42
Figure 43
52
At recommended operating conditions (see
Output hold times:
JTAG external clock to output high impedance:
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of t
2. The symbols used for timing specifications follow the pattern of t
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to t
5. Non-JTAG signal output timing with respect to t
6. Guaranteed by design and characterization.
The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
inputs and t
timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t
going to the high (H) state or setup time. Also, t
(D) went invalid (X) relative to the t
symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the
latter convention is used with the appropriate letter: R (rise) or F (fall).
provides the AC test load for TDO and the boundary-scan outputs.
provides the JTAG clock input timing diagram.
provides the TRST timing diagram.
Table 48. JTAG AC Timing Specifications (Independent of SYS_CLK_IN)
(first two letters of functional block)(reference)(state)(signal)(state)
External Clock
TRST
MPC8313E PowerQUICC
Parameter
JTAG
Output
Figure 41. AC Test Load for the JTAG Interface
JTG
Figure 42. JTAG Clock Input Timing Diagram
Boundary-scan data
Boundary-scan data
Table
VM
clock reference (K) going to the high (H) state. Note that, in general, the clock reference
t
JTKHKL
Figure 43. TRST Timing Diagram
2).
VM
VM = Midpoint Voltage (NV
VM = Midpoint Voltage (NV
TCLK
JTDXKH
™
Z
t
TCLK
JTG
0
II Pro Processor Hardware Specifications, Rev. 3
= 50 Ω
.
VM
TDO
TDO
.
symbolizes JTAG timing (JT) with respect to the time data input signals
t
TRST
Symbol
t
t
t
t
JTKLDX
JTKLOX
JTKLDZ
JTKLOZ
(first two letters of functional block)(signal)(state)(reference)(state)
VM
for outputs. For example, t
2
DD
DD
R
/2)
/2)
L
VM
= 50 Ω
Min
TCLK
t
2
2
2
2
JTGR
to the midpoint of the signal in question.
NV
DD
JTDVKH
Max
t
JTGF
/2
19
—
—
9
1
(continued)
symbolizes JTAG device
Freescale Semiconductor
JTG
clock reference (K)
Unit
Figure
ns
ns
34).
Notes
5, 6
for
5