MPC8313EVRAFFB Freescale Semiconductor, MPC8313EVRAFFB Datasheet - Page 82

IC MPU POWERQUICC II PRO 516PBGA

MPC8313EVRAFFB

Manufacturer Part Number
MPC8313EVRAFFB
Description
IC MPU POWERQUICC II PRO 516PBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8313EVRAFFB

Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
333MHz
Voltage
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Package / Case
516-PBGA
Processor Series
MPC8xxx
Core
e300
Data Bus Width
32 bit
Development Tools By Supplier
MPC8313E-RDB
Maximum Clock Frequency
400 MHz
Operating Supply Voltage
- 0.3 V to + 1.26 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
16 KB
I/o Voltage
2.5 V
Interface Type
I2C, SPI, UART
Minimum Operating Temperature
- 40 C
Program Memory Type
EEPROM/Flash
For Use With
MPC8313E-RDB - BOARD PROCESSOR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8313EVRAFFB
Manufacturer:
FREESCAL
Quantity:
150
Part Number:
MPC8313EVRAFFB
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Thermal
20.3
Table 69
reference frequencies, with RCWLR[LBCM] = 0 and RCWLR[DDRCM] =1, such that the LBC operates
with a frequency equal to the frequency of csb_clk and the DDR controller operates at twice the frequency
of csb_clk.
21 Thermal
This section describes the thermal specifications of the MPC8313E.
21.1
Table 70
82
Junction-to-ambient natural convection
Junction-to-ambient natural convection
Junction-to-ambient (@200 ft/min)
Junction-to-ambient (@200 ft/min)
Junction-to-board
1
2
3
4
5
6
PCI_CLK
CLK_IN/
System PLL multiplication factor.
System PLL VCO divider.
When considering operating frequencies, the valid core VCO operating range of 400–800 MHz must not be violated.
Due to erratum eTSEC40, csb_clk frequencies of less than 133 MHz do not support gigabit Ethernet data rates. The core
frequency must be 333 MHz for gigabit Ethernet operation. This erratum will be fixed in revision 2 silicon.
Frequency of USB PLL input reference.
USB reference clock must be supplied from a separate source as it must be 24 or 48 MHz, the USB reference must be
supplied from a separate external source using USB_CLK_IN.
SYS_
25.0
25.0
33.3
33.3
48.0
66.7
shows several possible frequency combinations that can be selected based on the indicated input
provides the package thermal characteristics for the 516, 27 × 27 mm TEPBGAII.
Example Clock Frequency Combinations
Thermal Characteristics
SPMF
Characteristic
6
5
5
4
3
2
1
VCOD
MPC8313E PowerQUICC
2
2
2
2
2
2
2
Table 70. Package Thermal Characteristics for TEPBGAII
VCO
600.0
500.0
666.0
532.8
576.0
533.4
3
( csb_clk )
Table 69. System Clock Frequencies
150.0
125.0
166.5
133.2
144.0
133.3
CSB
Four layer board (2s2p)
Four layer board (2s2p)
Single layer board (1s)
Single layer board (1s)
4
II Pro Processor Hardware Specifications, Rev. 3
(ddr_clk)
300.0
250.0
333.0
266.4
288.0
266.7
Board Type
DDR
62.5 31.25 15.6
66.6 33.3 16.7
66.7 33.34 16.7
/2
41.63 20.8
37.5 18.8
LBC(lbc_clk)
36
/4
18.0
Symbol
/8
R
R
R
R
R
θJMA
θJMA
θJA
θJA
θJB
Note 6
Note 6
Note 6
Note 6
Note
USB
48.0
ref
5
6
TEPBGA II
150.0
125.0
166.5
133.2
144.0
133.3
× 1
25
18
20
15
10
e300 Core(core_clk)
× 1.5
225
188
250
200
216
200
Freescale Semiconductor
300
250
333
266
288
267
°C/W
°C/W
°C/W
°C/W
°C/W
× 2
Unit
× 2.5
375
313
333
360
333
Notes
1, 2, 3
1, 2
1, 3
1, 3
375
400
400
4
× 3

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