ADAU1361BCPZ Analog Devices Inc, ADAU1361BCPZ Datasheet
ADAU1361BCPZ
Specifications of ADAU1361BCPZ
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ADAU1361BCPZ Summary of contents
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FEATURES 24-bit stereo audio ADC and DAC: >98 dB SNR Sampling rates from 8 kHz to 96 kHz Low power record playback, 48 kHz at 1 analog input pins, configurable for single-ended or differential ...
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ADAU1361 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications..................................................................................... 4 Analog Performance Specifications ........................................... 4 Power Supply Specifications........................................................ 7 Typical Current Consumption.................................................... 8 Typical Power Management ...
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REVISION HISTORY 9/10—Rev Rev. C Changes to Figure 1...........................................................................1 5/10—Rev Rev. B Changes to Burst Mode Writing and Reading Section ..............38 Changes to Table 26 ........................................................................45 Change to Table 43..........................................................................58 Added R67: Dejitter Control, 16,438 (0x4036) ...
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ADAU1361 SPECIFICATIONS Supply voltage (AVDD 25°C, master clock = 12.288 MHz (48 kHz f A bandwidth = kHz, word width = 24 bits, C unless otherwise noted. Performance of all channels ...
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Parameter PSEUDO-DIFFERENTIAL PGA INPUT Full-Scale Input Voltage (0 dB) Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Total Harmonic Distortion + Noise Signal-to-Noise Ratio With A-Weighted Filter (RMS) No Filter (RMS) Volume Control Step Volume Control Range PGA Boost ...
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ADAU1361 Parameter Interchannel Isolation Common-Mode Rejection Ratio MICROPHONE BIAS Bias Voltage 0.65 × AVDD 0.90 × AVDD Bias Current Source Noise in the Signal Bandwidth DIGITAL-TO-ANALOG CONVERTERS DAC Resolution Digital Attenuation Step Digital Attenuation Range DAC TO LINE OUTPUT Full-Scale ...
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Parameter DAC TO HEADPHONE/EARPIECE OUTPUT Full-Scale Output Voltage (0 dB) Total Harmonic Distortion + Noise 16 Ω load 32 Ω load Power Supply Rejection Ratio Interchannel Isolation REFERENCE Common-Mode Reference Output POWER SUPPLY SPECIFICATIONS Table 2. Parameter SUPPLIES Voltage Digital ...
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ADAU1361 TYPICAL CURRENT CONSUMPTION Master clock = 12.288 MHz, input sample rate = 48 kHz, input tone = 1 kHz, normal power management settings, ADC input @ −1 dBFS, DAC input @ 0 dBFS. For total power consumption, add the ...
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TYPICAL POWER MANAGEMENT MEASUREMENTS Master clock = 12.288 MHz, integer PLL, input sample rate = 48 kHz, input tone = 1 kHz. Pseudo-differential input to ADCs, DACs to line output with 10 kΩ load. ADC input @ −1 dBFS, DAC ...
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ADAU1361 DIGITAL FILTERS Table 5. Parameter ADC DECIMATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay DIGITAL INPUT/OUTPUT SPECIFICATIONS −40°C ...
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DIGITAL TIMING SPECIFICATIONS −40°C < T < +85°C, IOVDD = 3.3 V ± 10%. A Table 7. Digital Timing Parameter t MIN MASTER CLOCK 24 18.5 MP SERIAL PORT t 5 ...
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ADAU1361 DIGITAL TIMING DIAGRAMS t BIH BCLK t BIL t LIS LRCLK t SIS DAC_SDATA LEFT-JUSTIFIED MSB MODE t SIH DAC_SDATA MODE DAC_SDATA RIGHT-JUSTIFIED MODE 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 14-BIT CLOCKS (18-BIT DATA) ...
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CLS t CLATCH CCPH CCLK CDATA t CDS COUT t SCH SDA t SCL CLK DATA1/ DATA2 DATA1 t CCPL t CDH Figure 4. SPI Port Timing SCR SCLH SCS SCLL SCF 2 ...
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ADAU1361 ABSOLUTE MAXIMUM RATINGS Table 8. Parameter Power Supply (AVDD) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range Storage Temperature Range Stresses above those listed under Absolute Maximum Ratings may ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 10. Pin Function Descriptions 1 Pin No. Mnemonic Type 1 IOVDD PWR 2 MCLK D_IN 3 ADDR0/CLATCH D_IN 4 JACKDET/MICIN D_IN 5 MICBIAS A_OUT 6 LAUX A_IN 7 CM A_OUT 8 AVDD PWR 9 ...
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ADAU1361 1 Pin No. Mnemonic Type 19 RHP A_OUT 20 LHP A_OUT 21 MONOOUT A_OUT 22 AGND PWR 23 AVDD PWR 24 DVDDOUT PWR 25 DGND PWR 26 ADC_SDATA D_OUT 27 DAC_SDATA D_IN 28 BCLK D_IO 29 LRCLK D_IO 30 ...
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TYPICAL PERFORMANCE CHARACTERISTICS –60 –50 –40 –30 DIGITAL 1kHz INPUT SIGNAL (dBFS) Figure 8. Headphone Amplifier Power vs. Input Level, 16 Ω Load 18 16 ...
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ADAU1361 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 0 0.1 0.2 0.3 0.4 0.5 0.6 FREQUENCY (NORMALIZED TO Figure 14. ADC Decimation Filter, 128× Oversampling, Normalized −10 −20 −30 −40 −50 −60 −70 ...
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FREQUENCY (NORMALIZED TO Figure 20. DAC Interpolation Filter, 128× Oversampling, Normalized −10 −20 −30 −40 −50 −60 −70 −80 ...
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ADAU1361 SYSTEM BLOCK DIAGRAMS THE INPUT CAPACITOR VALUE DEPENDS ON THE INPUT IMPEDANCE, WHICH VARIES WITH THE VOLUME SETTING. 10µF LEFT MICROPHONE 10µF 2kΩ 2kΩ 10µF RIGHT MICROPHONE 10µF JACK DETECTION SIGNAL AUX LEFT 1kΩ AUX RIGHT 1kΩ CLOCK SOURCE ...
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THE INPUT CAPACITOR VALUE DEPENDS ON THE INPUT IMPEDANCE, WHICH VARIES WITH THE VOLUME SETTING 10µF SINGLE-ENDED ANALOG OUTPUT MICROPHONE CM GND V DD 10µF SINGLE-ENDED ANALOG OUTPUT MICROPHONE CM GND JACK DETECTION SIGNAL AUX LEFT 10µF 1kΩ ...
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ADAU1361 BCLK CLK CM DIGITAL MICROPHONE V DATA DD 0.1µF L/R SELECT GND BCLK CLK DIGITAL MICROPHONE V DATA DD 0.1µF L/R SELECT GND AUX LEFT 10µF 1kΩ 10µF AUX RIGHT 1kΩ 49.9Ω CLOCK SOURCE Figure 27. System Block Diagram ...
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THEORY OF OPERATION The ADAU1361 is an audio codec that offers high quality audio, low power, and small package size. The stereo ADC and stereo DAC each have an SNR of at least +98 dB and a THD + N ...
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ADAU1361 STARTUP, INITIALIZATION, AND POWER This section describes the procedure for properly starting up the ADAU1361. The following sequence provides a high level approach to the proper initiation of the system. 1. Apply power to the ADAU1361. 2. Lock the ...
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Case 2: PLL Is Used The core clock to the entire chip is off during the PLL lock acquisition period. The user can poll the lock bit to determine when the PLL has locked. After lock is acquired, the ADAU1361 ...
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ADAU1361 CLOCKING AND SAMPLING RATES R1: PLL CONTROL REGISTER MCLK ÷ X × N/M) CORE CLOCK Clocks for the converters and serial ports are derived from the core clock. The core clock can be derived directly from MCLK ...
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PLL The PLL uses the MCLK as a reference to generate the core clock. PLL settings are set in Register R1 (PLL control register, Address 0x4002). Depending on the MCLK frequency, the PLL must be set for either integer or ...
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ADAU1361 Table 16. Fractional PLL Parameter Settings for f MCLK Input (MHz) Input Divider ( 14.4 2 19.2 2 19. Table 17. Fractional PLL Parameter ...
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RECORD SIGNAL PATH JACKDET/MICIN PGA LINN –12dB TO LINP +35.25dB ALCSEL[2:0] LDVOL[5:0] ALC CONTROL LAUX RAUX PGA RINP –12dB TO RINN +35.25dB ALCSEL[2:0] RDVOL[5:0] ALC CONTROL INPUT SIGNAL PATHS The ADAU1361 can accept both line level and microphone inputs. The ...
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ADAU1361 Analog Microphone Inputs For microphone inputs, configure the part in either stereo pseudo-differential mode or stereo full differential mode. The LINN and LINP pins are the inverting and noninverting inputs for the left channel, respectively. The RINN and RINP ...
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Digital Microphone Input When using a digital microphone connected to the JACKDET/ MICIN pin, the JDFUNC[1:0] bits in Register R2 (Address 0x4008) must be set enable the microphone input and disable the jack detection function. The ADAU1361 ...
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ADAU1361 AUTOMATIC LEVEL CONTROL (ALC) The ADAU1361 contains a hardware automatic level control (ALC). The ALC is designed to continuously adjust the PGA gain to keep the recording volume constant as the input level varies. For optimal noise performance, the ...
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INPUT GAIN OUTPUT HOLD DECAY TIME TIME Figure 37. Basic ALC Operation MAX GAIN = 30dB MAX GAIN = 24dB MAX GAIN = 18dB TARGET INPUT LEVEL (dB) Figure 38. Effect of Varying the Maximum Gain Parameter NOISE GATE FUNCTION ...
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ADAU1361 Noise Gate Mode 2 (see Figure 41) is selected by setting the NGTYP[1:0] bits to 10. In this mode, the ADAU1361 improves the sound of the noise gate operation by first fading the PGA gain over a period of ...
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PLAYBACK SIGNAL PATH MX3G1[3:0] LEFT INPUT MIXER –15dB TO +6dB MX3G2[3:0] RIGHT INPUT MIXER –15dB TO +6dB MX3AUXG[3:0] LAUX –15dB TO +6dB LEFT DAC RIGHT DAC MX4G1[3:0] LEFT INPUT MIXER –15dB TO +6dB MX4G2[3:0] RIGHT INPUT MIXER –15dB TO +6dB ...
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ADAU1361 HEADPHONE OUTPUT The LHP and RHP pins can be driven by either a line output driver or a headphone driver by setting the HPMODE bit in Register R30 (playback headphone right volume control register, Address 0x4024). The headphone outputs ...
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Jack Detection When the JACKDET/MICIN pin is set to the jack detect func- tion, a flag on this pin can be used to mute the line outputs when headphones are plugged into the jack. This pin can be configured in ...
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ADAU1361 CONTROL PORTS The ADAU1361 can operate in one of two control modes: • control • SPI control The ADAU1361 has both a 4-wire SPI control port and a 2 2-wire I C bus control port. Both ...
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The R/ W bit determines the direction of the data. A Logic 0 on the LSB of the first byte means that the master will write infor- mation to the peripheral, whereas a Logic 1 means that the master will ...
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ADAU1361 Read and Write Operations Figure 50 shows the format of a single-word write operation. Every ninth clock pulse, the ADAU1361 issues an acknowledge by pulling SDA low. Figure 51 shows the format of a burst mode ...
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SPI PORT 2 By default, the ADAU1361 mode, but it can be put into SPI control mode by pulling CLATCH low three times. This is done by performing three dummy writes to the SPI port (the ...
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ADAU1361 SERIAL DATA INPUT/OUTPUT PORTS The flexible serial data input and output ports of the ADAU1361 can be set to accept or transmit data in 2-channel format 4-channel TDM stream to interface to external ADCs or DACs. ...
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LEFT CHANNEL LRCLK BCLK SDATA MSB LEFT CHANNEL LRCLK BCLK MSB SDATA Figure 58. Left-Justified Mode—16 Bits to 24 Bits per Channel LEFT CHANNEL LRCLK BCLK SDATA MSB Figure 59. Right-Justified Mode—16 Bits to 24 Bits per Channel LRCLK BCLK ...
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ADAU1361 APPLICATIONS INFORMATION POWER SUPPLY BYPASS CAPACITORS Each analog and digital power supply pin should be bypassed to its nearest appropriate ground pin with a single 100 nF capaci- tor. The connections to each side of the capacitor should be ...
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CONTROL REGISTERS Table 26. Register Map Reg Address Name Bit 7 R0 0x4000 Clock control R1 0x4002 PLL control Reserved R2 0x4008 Dig mic/jack detect R3 0x4009 Rec power mgmt Reserved R4 0x400A Rec Mixer Left 0 Reserved R5 0x400B ...
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ADAU1361 CONTROL REGISTER DETAILS All registers except for the PLL control register are 1-byte write and read registers. R0: Clock Control, 16,384 (0x4000) Bit 7 Bit 6 Bit 5 Reserved Table 27. Clock Control Register Bits Bit Name Description 3 ...
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Byte Bits Bit Name Description 4 [6:3] R[3:0] PLL integer setting. Setting 0010 0011 0100 0101 0110 0111 1000 4 [2:1] X[1:0] PLL input clock divider. Setting Type Type of PLL. When set to ...
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ADAU1361 R3: Record Power Management, 16,393 (0x4009) This register manages the power consumption for the record path. In particular, the current distribution for the mixer boosts, ADCs, record path mixers, and PGAs can be set to one of four modes. ...
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R4: Record Mixer Left (Mixer 1) Control 0, 16,394 (0x400A) This register controls the gain of single-ended inputs for the left channel record path. The left channel record mixer is referred to as Mixer 1. Bit 7 Bit 6 Bit ...
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ADAU1361 R5: Record Mixer Left (Mixer 1) Control 1, 16,395 (0x400B) This register controls the gain boost of the left channel differential PGA input and the gain for the left channel auxiliary input in the record path. The left channel ...
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R6: Record Mixer Right (Mixer 2) Control 0, 16,396 (0x400C) This register controls the gain of single-ended inputs for the right channel record path. The right channel record mixer is referred to as Mixer 2. Bit 7 Bit 6 Bit ...
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ADAU1361 R7: Record Mixer Right (Mixer 2) Control 1, 16,397 (0x400D) This register controls the gain boost of the right channel differential PGA input and the gain for the right channel auxiliary input in the record path. The right channel ...
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R9: Right Differential Input Volume Control, 16,399 (0x400F) This register enables the differential path and sets the volume control for the right differential PGA input. Bit 7 Bit 6 Bit 5 Table 36. Right Differential Input Volume Control Register Bits ...
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ADAU1361 R11: ALC Control 0, 16,401 (0x4011) Bit 7 Bit 6 Bit 5 PGASLEW[1:0] Table 38. ALC Control 0 Register Bits Bit Name Description [7:6] PGASLEW[1:0] PGA volume slew time when the ALC is off. The slew time is the ...
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R12: ALC Control 1, 16,402 (0x4012) Bit 7 Bit 6 Bit 5 ALCHOLD[3:0] Table 39. ALC Control 1 Register Bits Bit Name Description [7:4] ALCHOLD[3:0] ALC hold time. The ALC hold time is the amount of time that the ALC ...
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ADAU1361 R13: ALC Control 2, 16,403 (0x4013) Bit 7 Bit 6 Bit 5 ALCATCK[3:0] Table 40. ALC Control 2 Register Bits Bit Name Description [7:4] ALCATCK[3:0] ALC attack time. The attack time sets how fast the ALC starts attenuating after ...
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R14: ALC Control 3, 16,404 (0x4014) Bit 7 Bit 6 Bit 5 NGEN NGTYP[1:0] Table 41. ALC Control 3 Register Bits Bit Name Description [7:6] NGTYP[1:0] Noise gate type. When the input signal falls below the threshold for 250 ms, ...
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ADAU1361 R16: Serial Port Control 1, 16,406 (0x4016) Bit 7 Bit 6 Bit 5 BPF[2:0] Table 43. Serial Port Control 1 Register Bits Bit Name Description [7:5] BPF[2:0] Number of bit clock cycles per LRCLK audio frame. Setting 000 001 ...
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R17: Converter Control 0, 16,407 (0x4017) Bit 7 Bit 6 Bit 5 Reserved DAPAIR[1:0] Table 44. Converter Control 0 Register Bits Bit Name Description [6:5] DAPAIR[1:0] On-chip DAC serial data selection in TDM mode. Setting ...
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ADAU1361 R19: ADC Control, 16,409 (0x4019) Bit 7 Bit 6 Bit 5 Reserved ADCPOL HPF Table 46. ADC Control Register Bits Bit Name Description 6 ADCPOL Invert input polarity normal (default inverted. 5 HPF ADC high-pass ...
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R21: Right Input Digital Volume, 16,411 (0x401B) Bit 7 Bit 6 Bit 5 Table 48. Right Input Digital Volume Register Bits Bit Name Description [7:0] RADVOL[7:0] Controls the digital volume attenuation for right channel inputs from either the right ADC ...
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ADAU1361 R23: Playback Mixer Left (Mixer 3) Control 1, 16,413 (0x401D) Bit 7 Bit 6 Bit 5 MX3G2[3:0] Table 50. Playback Mixer Left (Mixer 3) Control 1 Register Bits Bit Name Description [7:4] MX3G2[3:0] Bypass gain control. The signal from ...
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R24: Playback Mixer Right (Mixer 4) Control 0, 16,414 (0x401E) Bit 7 Bit 6 Bit 5 Reserved MX4RM MX4LM Table 51. Playback Mixer Right (Mixer 4) Control 0 Register Bits Bit Name Description 6 MX4RM Mixer input mute. Mutes the ...
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ADAU1361 R25: Playback Mixer Right (Mixer 4) Control 1, 16,415 (0x401F) Bit 7 Bit 6 Bit 5 MX4G2[3:0] Table 52. Playback Mixer Right (Mixer 4) Control 1 Register Bits Bit Name Description [7:4] MX4G2[3:0] Bypass gain control. The signal from ...
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R26: Playback L/R Mixer Left (Mixer 5) Line Output Control, 16,416 (0x4020) Bit 7 Bit 6 Bit 5 Reserved Table 53. Playback L/R Mixer Left (Mixer 5) Line Output Control Register Bits Bit Name Description [4:3] MX5G4[1:0] Mixer input gain ...
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ADAU1361 R28: Playback L/R Mixer Mono Output (Mixer 7) Control, 16,418 (0x4022) Bit 7 Bit 6 Bit 5 Reserved Table 55. Playback L/R Mixer Mono Output (Mixer 7) Control Register Bits Bit Name Description [2:1] MX7[1:0] L/R mono playback mixer ...
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R30: Playback Headphone Right Volume Control, 16,420 (0x4024) Bit 7 Bit 6 Bit 5 Table 57. Playback Headphone Right Volume Control Register Bits Bit Name Description [7:2] RHPVOL[5:0] Headphone volume control for right channel, RHP output. Each 1-bit step corresponds ...
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ADAU1361 R32: Playback Line Output Right Volume Control, 16,422 (0x4026) Bit 7 Bit 6 Bit 5 Table 59. Playback Line Output Right Volume Control Register Bits Bit Name Description [7:2] ROUTVOL[5:0] Line output volume control for right channel, ROUTN and ...
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R34: Playback Pop/Click Suppression, 16,424 (0x4028) Bit 7 Bit 6 Bit 5 Reserved Table 61. Playback Pop/Click Suppression Register Bits Bit Name Description 4 POPMODE Pop suppression circuit power saving mode. The pop suppression circuits charge faster in normal operation; ...
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ADAU1361 R36: DAC Control 0, 16,426 (0x402A) Bit 7 Bit 6 Bit 5 DACPOL DACMONO[1:0] Table 63. DAC Control 0 Register Bits Bit Name Description [7:6] DACMONO[1:0] DAC mono mode. The DAC channels can be set to mono mode within ...
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R38: DAC Control 2, 16,428 (0x402C) Bit 7 Bit 6 Bit 5 Table 65. DAC Control 2 Register Bits Bit Name Description [7:0] RDAVOL[7:0] Controls the digital volume attenuation for right channel inputs from the right DAC. Each bit corresponds ...
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ADAU1361 R40: Control Port Pad Control 0, 16,431 (0x402F) The optional pull-up/pull-down resistors are nominally 250 kΩ. When enabled, these pull-up/pull-down resistors set the control port signals to a defined state when the signal source becomes three-state. Bit 7 Bit ...
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R42: Jack Detect Pin Control, 16,433 (0x4031) With IOVDD set to 3.3 V, the low and high drive strengths of the JACKDET/MICIN pin are approximately 2.0 mA and 4.0 mA, respectively. With IOVDD set to 1.8 V, the low and ...
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ADAU1361 Table 71. R8 and R9 Volume Settings Binary Value Volume Setting (dB) 000000 −12 000001 −11.25 000010 −10.5 000011 −9.75 000100 −9 000101 −8.25 000110 −7.5 000111 −6.75 001000 −6 001001 −5.25 001010 −4.5 001011 −3.75 001100 −3 001101 ...
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Table 73. R20, R21, R37, and R38 Volume Settings Binary Value Volume Attenuation (dB) 00000000 0 00000001 −0.375 00000010 −0.75 00000011 −1.125 00000100 −1.5 00000101 −1.875 00000110 −2.25 00000111 −2.625 00001000 −3 00001001 −3.375 00001010 −3.75 00001011 −4.125 00001100 −4.5 ...
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ADAU1361 Binary Value Volume Attenuation (dB) 01100000 −36 01100001 −36.375 01100010 −36.75 01100011 −37.125 01100100 −37.5 01100101 −37.875 01100110 −38.25 01100111 −38.625 01101000 −39 01101001 −39.375 01101010 −39.75 01101011 −40.125 01101100 −40.5 01101101 −40.875 01101110 −41.25 01101111 −41.625 01110000 −42 ...
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Binary Value Volume Attenuation (dB) 11000010 −72.75 11000011 −73.125 11000100 −73.5 11000101 −73.875 11000110 −74.25 11000111 −74.625 11001000 −75 11001001 −75.375 11001010 −75.75 11001011 −76.125 11001100 −76.5 11001101 −76.875 11001110 −77.25 11001111 −77.625 11010000 −78 11010001 −78.375 11010010 −78.75 11010011 ...
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ADAU1361 Binary Value Volume Setting (dB) 100001 −24 100010 −23 100011 −22 100100 −21 100101 −20 100110 −19 100111 −18 101000 −17 101001 −16 101010 −15 101011 −14 101100 −13 101101 −12 101110 −11 101111 −10 110000 −9 110001 −8 ...
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... MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE 1 Model Temperature Range ADAU1361BCPZ −40°C to +85°C ADAU1361BCPZ-R7 −40°C to +85°C ADAU1361BCPZ-RL −40°C to +85°C EVAL-ADAU1361Z RoHS Compliant Part. 5.00 BSC SQ 0.60 MAX 24 0.50 BSC TOP 4.75 VIEW BSC SQ ...
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ADAU1361 NOTES ©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07679-0-9/10(C) Rev Page ...