ADAU1361BCPZ Analog Devices Inc, ADAU1361BCPZ Datasheet - Page 40

• Manufacturer Part Number: ADAU1361BCPZ
• Description: IC CODEC 24B PLL 32LFCSP
• Manufacturer: Analog Devices Inc
• Type: Audio Codecr

Specifications of ADAU1361BCPZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• Voltage - Supply, Analog: 1.8 V ~ 3.6 V
• Voltage - Supply, Digital: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN, CSP Exposed Pad
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 7
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 101dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADAU1361
I
Figure 50 shows the format of a single-word write operation.
Every ninth clock pulse, the ADAU1361 issues an acknowledge
by pulling SDA low.
Figure 51 shows the format of a burst mode write sequence. This
figure shows an example of a write to sequential single-byte
registers. The ADAU1361 increments its subaddress register
after every byte because the requested subaddress corresponds
to a register or memory area with a 1-byte word length.
Figure 52 shows the format of a single-word read operation. Note
that the first R/ W bit is 0, indicating a write operation. This is
because the subaddress still needs to be written to set up the
internal address. After the ADAU1361 acknowledges the receipt
of the subaddress, the master must issue a repeated start command
followed by the chip address byte with the R/ W bit set to 1 (read).
S
S
S
S
2
C Read and Write Operations
Chip address,
R/W = 0
Chip address,
R/W = 0
Chip address,
R/W = 0
Chip address,
R/W = 0
AS
AS
AS
Subaddress
high byte
Subaddress
high byte
Subaddress high
byte
AS
Subaddress high byte
AS
AS
Subaddress
low byte
Subaddress
low byte
AS
Figure 50. Single-Word I
Figure 52. Single-Word I
Figure 51. Burst Mode I
Figure 53. Burst Mode I
Subaddress low
byte
Rev. C | Page 40 of 80
AS
AS
Data
Byte 1
AS
S
2
2
2
2
C Write Format
C Read Format
C Write Format
C Read Format
Chip address,
R/W = 1
This causes the ADAU1361 SDA to reverse and begin driving
data back to the master. The master then responds every ninth
pulse with an acknowledge pulse to the ADAU1361.
Figure 53 shows the format of a burst mode read sequence. This
figure shows an example of a read from sequential single-byte
registers. The ADAU1361 increments its subaddress register
after every byte because the requested subaddress corresponds
to a register or memory area with a 1-byte word length. The
ADAU1361 always decodes the subaddress and sets the auto-
increment circuit so that the address increments after the
appropriate number of bytes.
Figure 50 to Figure 53 use the following abbreviations:
S = start bit
P = stop bit
AM = acknowledge by master
AS = acknowledge by slave
Subaddress low byte
AS
AS
Data
Byte 2
S
AS
AS
Data
Byte 1
Chip address,
R/W = 1
Data
Byte 3
AS
AM
AS
Data Byte 1
Data
Byte 2
AS
Data
Byte 4
Data
Byte 1
AM
AS
…
…
P
P
P
P