ADAU1361BCPZ Analog Devices Inc, ADAU1361BCPZ Datasheet - Page 46

• Manufacturer Part Number: ADAU1361BCPZ
• Description: IC CODEC 24B PLL 32LFCSP
• Manufacturer: Analog Devices Inc
• Type: Audio Codecr

Specifications of ADAU1361BCPZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• Voltage - Supply, Analog: 1.8 V ~ 3.6 V
• Voltage - Supply, Digital: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN, CSP Exposed Pad
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 7
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 101dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADAU1361
CONTROL REGISTER DETAILS
All registers except for the PLL control register are 1-byte write and read registers.
R0: Clock Control, 16,384 (0x4000)
Bit 7
Table 27. Clock Control Register
Bits
3
[2:1]
0
R1: PLL Control, 16,386 (0x4002)
Byte
0
1
2
3
4
5
Table 28. PLL Control Register
Byte
0
1
2
3
Bits
[7:0]
[7:0]
[7:0]
[7:0]
Bit Name
CLKSRC
INFREQ[1:0]
COREN
Bit 7
Reserved
Bit 6
Bit Name
M[15:8]
M[7:0]
N[15:8]
N[7:0]
Description
Clock source select.
0 = direct from MCLK pin (default).
1 = PLL clock.
Input clock frequency. Sets the core clock rate that generates the core clock. If the PLL is used, this value is
automatically set to 1024 × f
Setting
00
01
10
11
Core clock enable. Only the R0 and R1 registers can be accessed when this bit is set to 0 (core clock disabled).
0 = core clock disabled (default).
1 = core clock enabled.
Reserved
Bit 6
Bit 5
Description
PLL denominator MSB. This value is concatenated with M[7:0] to make up a 16-bit number.
PLL denominator LSB. This value is concatenated with M[15:8] to make up a 16-bit number.
M[15:8] (MSB)
00000000
…
00000000
…
11111111
PLL numerator MSB. This value is concatenated with N[7:0] to make up a 16-bit number.
PLL numerator LSB. This value is concatenated with N[15:8] to make up a 16-bit number.
N[15:8] (MSB)
00000000
…
00000000
…
11111111
Bit 5
Bit 4
S
.
Reserved
R[3:0]
Input Clock Frequency
256 × f
512 × f
768 × f
1024 × f
Rev. C | Page 46 of 80
Bit 4
M[7:0] (LSB)
00000000
…
11111101
…
11111111
N[7:0] (LSB)
00000000
…
00001100
…
11111111
S
S
S
(default)
S
Bit 3
CLKSRC
M[15:8]
N[15:8]
M[7:0]
N[7:0]
Bit 3
Bit 2
Value of M
0
…
253 (default)
…
65,535
Value of N
0
…
12 (default)
…
65,535
Bit 2
INFREQ[1:0]
X[1:0]
Bit 1
Bit 1
Lock
Bit 0
COREN
Bit 0
Type
PLLEN