IDTSTAC9752AXTAED1X IDT, Integrated Device Technology Inc, IDTSTAC9752AXTAED1X Datasheet - Page 25

• Manufacturer Part Number: IDTSTAC9752AXTAED1X
• Description: IC CODEC AC'97 MIC/JACK 48-QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9752AXTAED1X

• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 85 / 92
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9752AXTAED1X

4.
IDT™
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
CONTROLLER, CODEC, AND AC-LINK
4.1.
4.2.
AC-Link Physical interface
Controller to Single CODEC
This section describes the physical and high-level functional aspects of the AC‘97 Controller to
CODEC interface, referred to as the AC-Link.
The STAC9752A/9753A communicates with its companion Digital Controller via the AC-Link digital
serial interface. AC-Link has been defined to support connections between a single Controller and
up to four CODECs. All digital audio, modem and handset data streams, as well as all control (com-
mand/status) information are communicated over this serial interconnect, which consists of a clock
(BIT_CLK), frame synchronization (SYNC), serial data in (SDATA_IN), serial data out
(SDATA_OUT), and a reset (RESET#).
The simplest and most common AC‘97 system configuration is a point-to-point AC-Link connection
between Controller and the STAC9752A/9753A, as illustrated in Figure 12.
A primary CODEC may act as either a source or a consumer of the BIT_CLK, depending on the con-
figuration.
While RESET# is asserted, if a clock is present at the BIT_CLK pin for at least five cycles before
RESET# is de-asserted, then the CODEC is a consumer of BIT_CLK, and must not drive BIT_CLK
when RESET# is de-asserted. The clock is being provided by other than the primary CODEC, for
instance by the controller or an independent clock chip. In this case the primary CODEC must act as
a consumer of the BIT_CLK signal as if it were a secondary CODEC.
This clock source detection must be done each time the RESET# line is asserted. In the case of a
warm reset, where the clock is halted but RESET# is not asserted, the CODEC must remember the
clock source, and not begin generating the clock on the assertion of SYNC if the CODEC had previ-
ously determined that it was a consumer of BIT_CLK.
The STAC9752A/9753A uses the XTAL_OUT pin (Pin 3) and the CID0 and CID1 pins (Pins 45 & 46)
to determine its alternate clock frequencies. See section2.2.4: page 17 for additional information on
Crystal Elimination and for supported clock frequencies.
Digital DC'97
Controller
Figure 12. AC-Link to its Companion Controller
S D A T A _ O U T
SDATA_IN
BIT_CLK
R E S E T #
S Y N C
25
AC'97 Codec
STAC9752A/9753A
XTAL_IN
X T A L _ O U T
PC AUDIO
V 1.5 1206