IDTSTAC9752AXTAED1X IDT, Integrated Device Technology Inc, IDTSTAC9752AXTAED1X Datasheet - Page 35

• Manufacturer Part Number: IDTSTAC9752AXTAED1X
• Description: IC CODEC AC'97 MIC/JACK 48-QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9752AXTAED1X

• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 85 / 92
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9752AXTAED1X

IDT™
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
5.3.
AC-Link Output Frame (SDATA_OUT)
2. Places a non-zero value (01, 10, or 11) into the CODEC ID field (Slot 0, bits 1 and 0).
3. Transmits the desired Secondary CODEC Command Address and Command Data in Slots 1
Secondary CODECs disregard the Command Address and Command Data (Slot 0, bits 14 and 13)
tag bits. In a sense the Secondary CODEC ID field functions as an alternative Valid Command
Address (for Secondary reads and writes) and Command Data (for Secondary writes) tag indicator.
Secondary CODECs must monitor the Frame Valid bit, and ignore the frame (regardless of the state
of the Secondary CODEC ID bits) if it is not valid. AC‘97 Digital Controllers should set the frame valid
bit for a frame with a Secondary register access, even if no other bits in the output tag slot except the
Secondary CODEC ID bits are set.
The AC-Link output frame data streams correspond to the multiplexed bundles of all digital output
data targeting AC‘97’s DAC inputs, and control registers. As mentioned earlier, each AC-Link output
frame supports up to twelve 20-bit outgoing data time slots. Slot 0 is a special reserved time slot
containing 16-bits which are used for AC-Link protocol infrastructure.
Figure 15 illustrates the time slot based AC-Link protocol.
A new AC-Link output frame begins with a low to high transition of SYNC. SYNC is synchronous to
the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the AC‘97
CODEC samples the assertion of SYNC. This falling edge marks the time when both sides of
AC-Link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC‘97 Con-
troller transitions SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit posi-
tion is presented to AC-Link on a rising edge of BIT_CLK, and subsequently sampled by the AC‘97
CODEC on the following falling edge of BIT_CLK. This sequence ensures that data transitions and
subsequent sample points for both incoming and outgoing data streams are time aligned.
SDATA_OUT’s composite stream is MSB justified (MSB first) with all non-valid slots’ bit positions
stuffed with 0s by the AC‘97 Controller. If there are less than 20 valid bits within an assigned and
SDATA_OUT
BIT_CLK
and 2.
End of previous audio frame
SYNC
12.288 MHz
Figure 16. Start of an Audio Output Frame
Frame
valid
Figure 15. AC-Link Audio Output Frame
slot1
Tag Phase
slot2
("1" = time slot contains valid PCM data)
Time Slot "Valid" Bits
slot(12)
"0"
35
CID1
CID0
19
Slot 1
"0"
19
STAC9752A/9753A
Slot 2
20.8 uS (48 kHZ)
Data Phase
"0"
19
Slot 3
"0"
PC AUDIO
19
Slot 12
V 1.5 1206
"0"