IDTSTAC9766XXTAEC1X IDT, Integrated Device Technology Inc, IDTSTAC9766XXTAEC1X Datasheet - Page 25

• Manufacturer Part Number: IDTSTAC9766XXTAEC1X
• Description: IC CODEC AC'97 2CH 2.3 48-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9766XXTAEC1X

• Data Interface: Serial
• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 85 / 95
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9766XXTAEC1X

1.
IDT™
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
STAC9766/9767
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
Secondary CODEC always configures its BIT_CLK pin as an input.
4.5.3.
4.5.4.
AC-link protocol provides for a “Cold AC‘97 Reset”, and a “Warm AC‘97 Reset”. The current power
down state would ultimately dictate which form of AC‘97 reset is appropriate. Unless a “cold” or “reg-
ister” reset (a write to the Reset Register) is performed, wherein the AC‘97 registers are initialized to
their default values, registers are required to keep state during all power down modes.
Once powered down, re-activation of the AC-link via re-assertion of the SYNC signal must not occur
for a minimum of four audio frame times following the frame in which the power down was triggered.
When AC-link powers up the CODEC indicates readiness via the CODEC Ready bit (input slot 0, bit
15).
CODEC Triggers Wake-up
The STAC9766/9767 (running off Vaux) can trigger a wake event (PME#) by transitioning
SDATA_IN from low to high and holding it high until either a warm or cold reset is observed on the
AC-link. This functionality is typically implemented in modem CODECs that detect ring, Caller ID,
etc.
Note that when the AC-link is either programmed to the low power mode or shut off completely,
BIT_CLK may stop if the primary CODEC is supplying the clock, which shuts down the AC-link clock
to the Secondary CODEC
ringing), it must support an independent clocking scheme for any PME# associated logic that must
be kept alive when the AC-link is down. This includes logic to asynchronously drive SDATA_IN to a
logic high-level which signals a wake request to the AC‘97 Digital Controller.
CODEC Reset
There are three types of AC‘97 reset:
•
•
•
4.5.4.1.
A cold reset is achieved by asserting RESET# low for the minimum specified time, then subse-
quently de-asserting RESET# high. BIT_CLK and SDATA_IN will be activated, or re-activated as the
case may be, and all AC‘97 control registers will be initialized to their default power-on reset values.
RESET# is an asynchronous AC‘97 input.
4.5.4.2.
A warm AC‘97 reset will re-activate the AC-link without altering the current AC‘97 register values. A
warm reset is signaled by driving SYNC high for a minimum of 1 s in the absence of BIT_CLK.
A cold reset where all AC‘97 logic (most registers included) is initialized to its default state.
A warm reset where the contents of the AC‘97 register set are left unaltered.
A register reset which only initializes the AC‘97 registers to their default states.
Cold AC‘97 Reset
Warm AC‘97 Reset
1
. In order for a Secondary CODEC to react to an external event (phone
25
STAC9766/9767
PC AUDIO
V 7.4 12/06