IDTSTAC9766XXTAEC1X IDT, Integrated Device Technology Inc, IDTSTAC9766XXTAEC1X Datasheet - Page 65

• Manufacturer Part Number: IDTSTAC9766XXTAEC1X
• Description: IC CODEC AC'97 2CH 2.3 48-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9766XXTAEC1X

• Data Interface: Serial
• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 85 / 95
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9766XXTAEC1X

IDT™
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
STAC9766/9767
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
8.2.
General Purpose Input & Outputs
8.2.1.
8.2.2.
8.2.3.
EAPD
EAPD can act as a GPIO, but is unaffected by the following registers. To use EAPD as a GPIO, use
Register 74h, the EAPD Access Register (see Section8.4.11: page78). Additional information
about EAPD can also be found in Section 8.1.18.3: page 59.
GPIO Pin Definitions
GPIO pins are programmable to have input/output functionality. The data values (status) for these
pins are all in one register with input/output configuration in a separate register. Control of GPIO pins
configured for output is achieved by setting the corresponding bit in output slot 12; status of GPIO
pins configured for input is returned on input slot 12. The CODEC must constantly set the GPIO pins
that are configured for output, based upon the value of the corresponding bit position of the control
slot 12. The CODEC should ignore output slot 12 bits that correspond to GPIO control pins config-
ured as inputs. The CODEC must constantly update status on input slot 12, based upon the logic
level detected at each GPIO pin configured for input. A GPIO output pin value that is written via slot
12 in the current frame will not affect the GPIO status that is returned in that particular write frame.
This slot-12 based control/status protocol minimizes the latency and complexity, especially for
host-based Controllers and host data pump software, and provides high speed monitoring and con-
trol, above what could be achieved with command/status slots. For host-based implementations,
most AC‘97 registers can be shadowed by the driver in order to provide immediate response when
read by the processor, and GPIO pins configured as inputs should be capable of triggering an inter-
rupt upon a change of status.
The AC-link request for GPIO pin status is always delayed by at least one frame time. Read-Mod-
ify-Writes across the AC-link incur latency issues which must be accounted for by the software driver
or AC‘97 Digital Controller firmware. PCI retries should be kept to a minimum wherever possible.
GPIO Pin Implementation
The GPIOs are set to a high impedance state on power-on or a cold reset. It is up to the AC‘97 Digi-
tal Controller to first enable the output after setting it to the desired state.
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STAC9766/9767
PC AUDIO
V 7.4 12/06