IDTSTAC9766XXTAEC1X IDT, Integrated Device Technology Inc, IDTSTAC9766XXTAEC1X Datasheet - Page 85

• Manufacturer Part Number: IDTSTAC9766XXTAEC1X
• Description: IC CODEC AC'97 2CH 2.3 48-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9766XXTAEC1X

• Data Interface: Serial
• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 85 / 95
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9766XXTAEC1X

11.TESTABILITY
IDT™
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
STAC9766/9767
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
11.1. ATE Test Mode
The STAC9766/9767 has two test modes. One is for ATE in-circuit test and the other is restricted for
IDT’s internal use. STAC9766/9767 enters the ATE in-circuit test mode if SDATA_OUT is sampled
high at the trailing edge of RESET#. Once in the ATE test mode, the digital AC-Link outputs
(BIT_CLK and SDATA_IN) are driven to a high impedance state. This allows ATE in-circuit testing of
the AC'97 controller. Use of the ATE test mode is the recommended means of removing the CODEC
from the AC-Link when another CODEC is to be used as the primary. This case will never occur dur-
ing standard operating conditions. Once either of the two test modes have been entered, the
STAC9766/9767 must be issued another RESET# with all AC-link signals held low to return to the
normal operating mode.
ATE test mode allows for in-circuit testing to be completed at the board level. For this to work, the
outputs of the device must be driven to a high impedance state (Z). Internal pullups for digital I/O
pins must be disabled in this mode. This mode initiates on the rising edge of RESET# pin. Only a
cold reset will exit the ATE Test Mode.
SDATA_OUT
No Connect
No Connect
No Connect
SDATA_IN
Pin Name
BIT_CLK
SYNC
RESET#
GPIO0
GPIO1
SPDIF
SYNC
EAPD
CID0
CID1
0
0
1
1
SDATA_OUT
Pin #
10
11
31
33
34
43
44
45
46
47
48
5
6
8
0
1
0
1
Table 33. ATE Test Mode Operation
Table 32. Test Mode Activation
85
Function
1
Z
Z
0
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Must be held high at the rising edge of RESET#
Must be held low at rising edge of RESET#
Always an input
Always an input
Always an input
Normal AC '97 operation
IDT Internal Test Mode
STAC9766/9767
ATE Test Mode
Description
Reserved
Description
PC AUDIO
V 7.4 12/06