EMC2303-1-KZ-TR SMSC, EMC2303-1-KZ-TR Datasheet - Page 73
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EMC2303-1-KZ-TR
Manufacturer Part Number
EMC2303-1-KZ-TR
Description
Industrial Temperature Sensors RPM B Fan Controller w/HW Thermal Shutdwn
Manufacturer
SMSC
Datasheet
1.EMC2300-AZC-TR.pdf
(82 pages)
Specifications of EMC2303-1-KZ-TR
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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- Download datasheet (2Mb)
Fan Control Device with High Frequency PWM and Temperature Monitors
Datasheet
SMSC EMC2300
8.2.28
Register
Address
BIT
0
1
2
3
4
5
6
7
94h
95h
96h
NAME
SLOW
MODE
Read/
EDG0
EDG1
3EDG
Write
R/W
R/W
R/W
RES
RES
RES
Registers 94h-96h: PWMx Option Registers
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PWM1 Option
PWM2 Option
PWM3 Option
Register
Name
Table 8.53 Registers 94h-96h: PWMx Option Registers
DEFAULT
0
0
1
0
0
0
0
0
Table 8.52 TACH Option Register Bits
Determines the number of edges necessary for a valid TACH reading.
Determines TACH reading mode
This bit is used when the TACH Mode is configured for Mode 2 only.
Note:
Reserved
Reserved
Reserved
‘0’ - Force TACH reading register to FFFEh if number of tach edges
detected is greater than 0 but less than the programmed number of
edges
‘1’ - Force TACH reading register to FFFFh if number of tach edges
detected is greater than 0 but less than the programmed number of
edges
00 = 2 edges
01 = 3 edges
10 = 5 edges
11 = 9 edges
‘0’ Mode 1 - standard operating mode
‘1’ Mode 2 - only check measure TACH while PWM output is high.
‘0’ - don’t ignore 1st 3 TACH edges after PWM transitions from low to
high
‘1’ - ignore first 3 edges after guard time
(MSb)
Bit 7
RES
RES
RES
DATASHEET
This bit has been added to support a small sampling of fans that
emit irregular tach pulses when the PWM transitions ‘ON’.
Typically, the guard time is sufficient for most fans.
Bit 6
RES
RES
RES
73
Bit 5
OPP
OPP
OPP
GRD1
GRD1
GRD1
Bit 4
DESCRIPTION
GRD0
GRD0
GRD0
Bit 3
SZEN
SZEN
SZEN
Bit 2
UPDT1
UPDT1
UPDT1
Bit 1
Revision 0.32 (06-23-08)
UPDT0
UPDT0
UPDT0
(LSb)
Bit 0
Default
Value
0Ch
0Ch
0Ch
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