TDA8029HL/C207,118 NXP Semiconductors, TDA8029HL/C207,118 Datasheet - Page 36

IC SMART CARD READER 32-LQFP

TDA8029HL/C207,118

Manufacturer Part Number
TDA8029HL/C207,118
Description
IC SMART CARD READER 32-LQFP
Manufacturer
NXP Semiconductors
Datasheet

Specifications of TDA8029HL/C207,118

Package / Case
32-LQFP
Controller Type
Smart Card Reader Interface
Interface
Serial
Voltage - Supply
2.7 V ~ 6 V
Current - Supply
250mA
Operating Temperature
-40°C ~ 90°C
Mounting Type
Surface Mount
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-2233-2
935274733118
TDA8029HL07BD-T

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TDA8029HL/C207,118
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
TDA8029HL/C207,118
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Philips Semiconductors
Table 58:
Table 59:
Table 60:
Table 61:
9397 750 14145
Product data sheet
Bit
7 to 0
Bit
7
6
5
4
3
2
1
0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
PDR - programmable divider register (address 2h) bit allocation
PDR - programmable divider register (address 2h) bit description
UCR2 - UART configuration register 2 (address 3h) bit allocation
UCR2 - UART configuration register 2 (address 3h) bit description
8.10.3.2 UART configuration register 2 (UCR2)
Symbol
PD[7:0]
Symbol
ENINT1
DISTBF/RBF
-
ENRX
SAN
AUTOCONV
CKU
PSC
ENINT1
PD7
7
0
7
0
DISTBE/RBF
PD6
6
0
Description
Programmable divider value.
6
0
Description
Enable INT1. If ENINT1 = 1, a HIGH to LOW transition on pin INT1_N will wake-up the
TDA8029 from the Power-down mode. Note that in case of reception of a character when
in Power-down mode, the start of the frame will be lost. When not in Power-down mode
ENINT1 has no effect. For details on Power-down mode see
Disable TBE/RBF interrupts. If DISTBE/RBF is set, then reception or transmission of a
character will not generate an interrupt. This feature is useful for increasing
communication speed with the card; in this case, the copy of TBE/RBF bit within MSR
must be polled, and not the original, in order not to loose priority interrupts which can
occur in USR.
Not used.
Enable RX. If ENRX = 1, a HIGH to LOW transition on pin RX will wake-up the TDA8029
from the Power-down mode. Note that in case of reception of a character when in
Power-down mode, the start of the frame will be lost. When not in Power-down mode
ENRX has no effect. For details on Power-down mode see
Synchronous or asynchronous. SAN is set by software if a synchronous card is
expected. The UART is then bypassed and only bit 0 in registers URR and UTR is
connected to pin I/O. In this case the clock is controlled by bit SC in register CCR.
Automatic set convention. If AUTOCONV = 1, then the convention is set by software
using bit CONV in register UCR1. If AUTOCONV = 0, then the configuration is
automatically detected on the first received character whilst the start session (bit SS) is
set. AUTOCONV must not be changed during a card session.
Clock Unit. For baud rates other than those given in
set bit CKU = 1. In this case, the ETU will last half the number of card clock cycles equal
to prescaler PDR. Note that bit CKU = 1 has no effect if f
example, that 76800 baud is not possible when the card is clocked with the frequency on
pin XTAL1.
Prescaler value. If PSC = 1, then the prescaler value is 32; if PSC = 0, then the prescaler
value is 31. One ETU will last a number of card clock cycles equal to prescaler
All baud rates specified in ISO 7816 norm are achievable with this configuration. See
Figure 10
and
PD5
5
0
Rev. 03 — 22 February 2005
Table
5
-
-
62.
PD4
ENRX
4
0
read and write
read and write
4
0
PD3
SAN
3
0
3
0
AUTOCONV
Table
PD2
Low power single card reader
2
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
2
0
CLK
62, there is the possibility to
Section
= f
Section 8.15
XTAL
PD1
. This means, for
8.15.
1
0
TDA8029
CKU
1
0
PD0
PSC
PDR.
0
0
36 of 59
0
0

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