TMC2074-NU SMSC, TMC2074-NU Datasheet - Page 59

• Manufacturer Part Number: TMC2074-NU
• Description: IC CTRL CIRC 128VTQFP PERIPH MOD
• Manufacturer: SMSC
• Series: CircLink™r

Specifications of TMC2074-NU

• Controller Type: I/O Controller
• Interface: Transceiver
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1024

Dual Mode CircLink™ Controller
Datasheet
SMSC TMC2074
A possible cause of unlock status not being cancelled is that the CM node’s NST pre-scalar setting is not
synchronized. A possible cause of sometimes falling into unlock status is that the CM node’s transmission
frequency is low.
In the case of CM node, the flag becomes 0 in a steady state (synchronous lock status) for no apparent
reason. As the initial settings in this case depends on the function modes, listed below:
In Peripheral mode, the CM node ID is set in a register after cancellation of Hardware Reset. After these
values are imported, the output is 1 until the node becomes a CM node (it becomes 0 after that). During
Software Reset, due to the CM Node ID being immediately imported, the CM Node ID is fixed at 1and
transitioning to 0 immediately after being set up in the register.
In standalone mode, the CM node ID is a pin setting; when it is the same setting as the CM node setting,
output is 1 during Hardware Reset, and 0 when Hardware Reset is cancelled.
Unlock Phase difference register
The phase difference between the NST in the CM node and the NST in the subject node can be monitored
through the NSTDIF register.
DIFDIR (NSTDIF register: bit 15)
Indicates the direction of phase difference
0: Ahead of CM node 1: Behind of CM node
NSTDIF 14-0 (NSTDIF register: bit 14-0)
Absolute difference from the CM node is indicated as a value from 0 to 32,768.
Accessing the NSTDIF register can dynamically provide the latest time data. Since NSTDIF is a 16 bit
value, it is necessary to read the even address side (32h) first when 8-bit bus is used. When the even
address is read out, the remaining 8 bits of the NST are latched internally.
DATASHEET
Page 59
Revision 0.2 (10-23-08)