TMC2074-NU SMSC, TMC2074-NU Datasheet - Page 94

• Manufacturer Part Number: TMC2074-NU
• Description: IC CTRL CIRC 128VTQFP PERIPH MOD
• Manufacturer: SMSC
• Series: CircLink™r

Specifications of TMC2074-NU

• Controller Type: I/O Controller
• Interface: Transceiver
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1024

NOTE:
Revision 0.2 (10-23-08)
TXEN (bit 8)
Setting this bit to 1 in CircLink enables network participation. The initial value differs depending on the
operation mode; the starting status is 0 = offline and 1 = online in the peripheral mode and the standalone
mode, respectively. This bit is the same as the TXEN bit in the COMR6 register. If this bit is rewritten from
0 to 1, software reset is automatically executed. (The software reset is released automatically.) The
software reset is not applied when the bit is changed from 1 to 0.
1: Online state, 0: Offline state
ECRI (bit 7)
This bit stops automatic issuing of receive commands to the ARCNET core. The CircLink always receives;
to stop receiving, set this bit to 1. Moreover, this bit returns NAK to the free buffer enquiry (FBE) to the bit.
Returning this bit from 1 to 0 sets the receive flag registers RXF01 to RXF31 to the (initial) value of 1.
When CircLink receives a token issued by itself, ECRI is set. This causes a delay because setting/clearing
ECRI affects reception flags RXF0-RXF3. The delay is 52 ms; when the network data rate is 2.5 Mbps, and
scales accordingly for other rates.
1: Normal stop, 0: Normal operation
The delay will be caused by the time the result of changing ECRI reflected internally. ECRI is reflected
when the token to oneself is received, and do the following processing, please after inserting the weight of
maximum value (52mS @2.5Mbps) at the time of token surroundings cycle when you change ECRI. 52mS
or less is delayed to the initialization operation of reception flag register RXF01-RXF31 when ECRI is
returned to 1→0.
52mS is a value for 2.5Mbps. This time depends on transfer rate. If it is 5Mbps, this time is half (26mS). If
it’s 1.25Mbps, it is two time (104mS).
BRE (bit 6)
1: Receives broadcast packet, 0: Not receive
TXM (bit 5)
1: Remote buffer sending mode, 0: Free format sending mode
RTO (bit 4)
This bit specifies the sending count in the remote buffer sending mode
1: Only one packet sending, 0: Continuous auto-sending
WDMD (bit 3)
This bit specifies the data structure mode to access data register (COMR4) through 8-bit bus. When this bit
is set to 1, to protect the higher and lower bytes of word data as one packet, it is necessary to perform an
access to COMR4 in the order of 08h to 09h. (Protection is unavailable in the order of 09h to 08h, 08h to
08h, and 09h to 09h) The rule is applicable for both write and read.
1: 16-bit data batch, 0: 8-bit data batch
DATASHEET
Page 94
Dual Mode CircLink™ Controller
SMSC TMC2074
Datasheet