TMC2074-NU SMSC, TMC2074-NU Datasheet - Page 85

• Manufacturer Part Number: TMC2074-NU
• Description: IC CTRL CIRC 128VTQFP PERIPH MOD
• Manufacturer: SMSC
• Series: CircLink™r

Specifications of TMC2074-NU

• Controller Type: I/O Controller
• Interface: Transceiver
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1024

Dual Mode CircLink™ Controller
Datasheet
SMSC TMC2074
CMIECC (bit 14)
This bit indicates that error correction of received data has been performed in the CMI decoding circuit. As
soon as this bit is set, the details of the error are stored in CMIEI3-0 (bits 11 to 8) of the ERRINFO register.
This bit is cleared by writing a 1 or by software reset.
NSTUNLOC (bit 13)
Indicates synchronizing with the CM node’s NST. This bit is set by Software Reset. For further details,
please refer to section 2.12.
0: Synchronous Lock status 1: Synchronous Unlock Status (Initial Value)
In the CM node, this flag goes into steady state 0 (Synchronous Lock status). Accordingly, the initial
settings are as detailed below:
In Peripheral mode, the CM node ID is set in a register after cancellation of Hardware Reset. After these
values are imported, the output is 1 until it assumes itself as a CM node (it becomes 0 after that). During
Software Reset, due to the CM Node ID being immediately imported, the CM Node ID is fixed at 1→0
immediately after set-up in the register.
In standalone mode, the CM node ID is the pin setting when it is the same setting as the CM node setting.
The output is 1 during Hardware Reset, and 0 when Hardware Reset is cancelled.
WARTERR (bit 12)
This bit is set if data is not received by any page set in remote buffer receive mode within a fixed period.
This bit is cleared by the WARTERR clear command or by a software reset.
1: No receive within a fixed period, 0: Receive within a fixed period
FRCV (bit 11)
This bit is set if the reception by any page set in free format receive mode is completed normally. This bit is
cleared by writing a 1 or by a software reset.
1: Receive complete, 0: Receive in progress
RRCV (bit 10)
This bit is set if the reception of any page set in remote buffer receive mode is completed normally. This bit
is cleared by writing a 1 or by a software reset.
1: Receive complete, 0: Receive in progress
MRCV (bit 9)
This bit is set if the reception of a packet sent to this node (DID = NID) is completed normally. This bit is
cleared by writing a 1 or by a software reset.
1: Receive complete, 0: Receive in progress
SIDF (bit 8)
This bit is set if a packet sent from the SID specified by the SSID register is received. This bit is cleared by
writing a 1or by a software reset.
DATASHEET
Page 85
Revision 0.2 (10-23-08)