FDC37C665GT-MS SMSC, FDC37C665GT-MS Datasheet - Page 108

IC CTRLR SUPER I/O MULTI 100-QFP

FDC37C665GT-MS

Manufacturer Part Number
FDC37C665GT-MS
Description
IC CTRLR SUPER I/O MULTI 100-QFP
Manufacturer
SMSC
Datasheet

Specifications of FDC37C665GT-MS

Controller Type
I/O Controller
Interface
ISA Host
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
35mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
638-1007

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
FDC37C665GT-MS
Manufacturer:
Microchip Technology
Quantity:
10 000
OPERATION
Mode Switching/Software Control
Software will execute P1284 negotiation and all
operation prior to a data transfer phase under
programmed I/O control (mode 000 or 001).
Hardware provides an automatic control line
handshake, moving data between the FIFO and
the ECP port only in the data transfer phase
(modes 011 or 010).
Setting the mode to 011 or 010 will cause the
hardware to initiate data transfer.
If the port is in mode 000 or 001 it may switch to
any other mode. If the port is not in mode 000
or 001 it can only be switched into mode 000 or
001. The direction can only be changed in
mode 001.
Once in an extended forward mode the software
should wait for the FIFO to be empty before
switching back to mode 000 or 001. In this case
all control signals will be deasserted before the
mode switch. In an
software waits for all the data to be read from
the FIFO before changing back to mode 000 or
001. Since the automatic hardware ecp reverse
handshake only cares about the state of the
FIFO it may have acquired extra data which will
be discarded. It may in fact be in the middle of a
transfer when the mode is changed back to 000
or 001. In this case the port will deassert
nAutoFd independent of the state of the transfer.
The design shall not cause glitches on the
handshake signals if the software meets the
constraints above.
ECP Operation
Prior to ECP operation the Host must negotiate
on the parallel port to determine if the peripheral
supports the ECP protocol. This is a somewhat
complex negotiation carried out under program
control in mode 000.
ecp
reverse mode the
108
After negotiation, it is necessary to initialize
some of the port bits. The following are required:
Ÿ
Ÿ
Ÿ
Ÿ
ECP address/RLE bytes or data bytes may be
sent automatically by writing the ecpAFifo or
ecpDFifo respectively.
Note that all FIFO data transfers are byte wide
and byte aligned.
byte-wide and only allowed in the forward
direction.
The host may switch directions by first switching
to mode = 001, negotiating for the forward or
reverse channel, setting
then setting mode = 011. When direction is 1
the hardware shall handshake for each ECP
read data byte and attempt to fill the FIFO.
Bytes may then be read from the ecpDFifo as
long as it is not empty .
ECP transfers may also be accomplished (albeit
slowly) by handshaking individual bytes under
program control in mode = 001, or 000.
Termination from ECP Mode
Termination from ECP Mode is similar to the
termination from Nibble/Byte Modes. The host is
permitted to terminate from ECP Mode only in
specific well-defined states. The termination can
only be executed while the bus is in the forward
direction. To terminate while the channel is in
the reverse direction, it must first be transitioned
into the forward direction.
Set Direction = 0, enabling the drivers.
Set strobe = 0, causing the nStrobe signal
to default to the deasserted state.
Set autoFd = 0, causing the nAutoFd signal
to default to the deasserted state.
Set mode = 011 (ECP Mode)
Address/RLE transfers are
direction to 1 or 0,

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