FDC37C665GT-MS SMSC, FDC37C665GT-MS Datasheet - Page 127

• Manufacturer Part Number: FDC37C665GT-MS
• Description: IC CTRLR SUPER I/O MULTI 100-QFP
• Manufacturer: SMSC

Specifications of FDC37C665GT-MS

• Controller Type: I/O Controller
• Interface: ISA Host
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 35mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1007

CR6
This register can only be accessed when the
FDC is in the Configuration Mode and after the
CSR has been initialized to 06H. The default
value of this register after power up is FFH. This
register holds the floppy disk drive types for up
to four floppy disk drives.
CR7
This register can only be accessed when the
FDC is in the Configuration Mode and after the
CSR has been initialized to 07H. The default
value of this register after power up is 00H. This
register holds the value for the floppy boot drive
and the polarity of the media ID bits.
CR8
This register can only be accessed when the
FDC is in the Configuration Mode and after the
CSR has been initialized to 08H. The default
value of this register after power up is 00H. This
is the lower 8 bits for the ADRx address decode.
(Note: All addresses are qualified with AEN.)
CR9
This register can only be accessed when the
FDC is in the Configuration Mode and after the
CSR has been initialized to 09H. The default
value of this register after power up is 00H. This
is the upper 3 bits (D2 - MSB, D0 - LSB) for the
ADRx address decode.
selected then A10 is assumed to be low. (Note:
All addresses are qualified with AEN.)
If ECP mode is not
127
CRA
This register can only be accessed when the
FDC is in the Configuration Mode and after the
CSR has been initialized to 0AH. The default
value of this register after power up is 00H. This
byte defines the FIFO threshold for the ECP
mode parallel port.
CRB and CRC
Reserved - The contents of these registers are
undefined when read.
CRD
This register can only be accessed when the
FDC is in the Configuration Mode and after the
CSR has been initialized to 0DH. This register
is read only. The default value of this register
after power up is 065H for the FDC37C665GT
and a 066H for the FDC37C666GT.
CRE
This register can only be accessed when the
FDC is in the Configuration Mode and after the
CSR has been initialized to 0EH. This register
is read only. The default value of this register
after power up is 02H. This is used to identify
the chip revision level.
CRF
This register can only be accessed when the
FDC is in the Configuration Mode and after the
CSR has been initialized to 0FH. The default
value of this register after power up is 00H.