TDA8026ET/C2,518 NXP Semiconductors, TDA8026ET/C2,518 Datasheet - Page 33

• Manufacturer Part Number: TDA8026ET/C2,518
• Description: IC SMART CARD SLOT 64TFBGA
• Manufacturer: NXP Semiconductors

Specifications of TDA8026ET/C2,518

• Controller Type: Smart Card Interface
• Interface: I²C
• Voltage - Supply: 2.7 V ~ 5.5 V
• Current - Supply: 210mA
• Operating Temperature: -25°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
TDA8026_1
Product data sheet
8.8.1 Standby mode
8.8.2 Activation sequence
Card slot 1 or card slot 2 can only be activated if a card is detected as present in the slot
and if an alarm is not triggered by the voltage supervisor. When both of these parameters
are met, the card slots can be activated by setting the Command register START bit. The
activation sequence is described in
Card slots 3 to 5 do not have presence monitoring. The corresponding STAP pin is used
for card presence detection on these slots.
The deactivation is initiated by the system controller or automatically in the case of a
hardware problem or a supply drop out. The deactivation sequence is described in
Section
Outside a session, the card contacts are forced to low-impedance with respect to the
GNDC pin.
Standby mode is the default state after a power-on reset. This mode ensures the power
consumption remains low until a card is inserted or the microcontroller starts a card
session. When there is not an ongoing card session, the internal oscillator runs at its low
frequency (t
A debouncing time of 17.8 ms is applied to card slot 1 and card slot 2 to allow for card
insertion (presence) detection.
When the card is inactive, pins V
low-impedance with respect to pin GNDC
The sequencer is clocked by an internal oscillator. When everything is satisfactory
(voltage supply, card presence, no hardware problem), the system controller can trigger
the card present activation sequence by setting card slot’s START bit to logic 1:
CLK
pin is managed by the ATR counter or the Register1 RSTIN bit depending on the card slot
mode (asynchronous or synchronous).
The sequencer is clocked by
Thus,
•
•
•
•
The internal oscillator switches to its high frequency (t
The DC-to-DC converter starts (t
V
The voltage on the I/O
V
(n)
CC(n)
CC(n)
t
clock signal is sent to the card (t
1
8.8.3.
=
starts to rise from 0 V to 1.8 V, 3 V or 5 V during the controlled rise time (t
(t
0
15
3
).
,
).
t
2
All information provided in this document is subject to legal disclaimers.
=
t
1
+
3T
------ -
Rev. 1 — 9 March 2010
2
,
(n)
t
3
pin rises to V
-------------------
f
=
osc int
64
t
CC(n)
1
+
Section
7T
------ -
1
2
, CLK
).
which leads to a time interval T = 25 s (typical).
4
and
= t
(n)
CC(n)
(n)
act
8.8.2.
or pin GNDS depending of the card slot.
t
, RST
4
) and the RST
, due to integrated 10 k pull-ups for
=
t
1
(n)
Multiple smart card slot interface IC
+
4T
and I/O
.
0
, see
(n)
(n)
pin is enabled. The RST
are LOW which is
Figure
TDA8026
© NXP B.V. 2010. All rights reserved.
10).
33 of 59
2
).
(n)