FDC37B727-NS SMSC, FDC37B727-NS Datasheet - Page 197
FDC37B727-NS
Manufacturer Part Number
FDC37B727-NS
Description
IC CTRLR SUPER I/O ENH 128-QFP
Manufacturer
SMSC
Datasheet
1.FDC37B727-NS.pdf
(238 pages)
Specifications of FDC37B727-NS
Controller Type
I/O Controller
Interface
ISA Host
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
30mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
638-1005
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
FDC37B727-NS
Manufacturer:
Standard
Quantity:
99
Company:
Part Number:
FDC37B727-NS
Manufacturer:
Microchip Technology
Quantity:
10 000
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ACPI, Logical Device A
Sleep/Wake
Configuration
Default = 0x00
on Vbat POR
NAME
Table 75 - ACPI, Logical Device A [Logical Device Number = 0x0A]
0xF0
REG INDEX
This register is used to configure the functionality of the
SLP_EN bit and its associated logic, and the WAK_STS
bit bit and its associated logic.
Bit[0] SLP_CTRL. SLP_EN Bit Function.
Note: the SLP_EN_SMI bit in the SMI Status Register 2
Bit[1] WAK_CTRL. WAK_STS Bit Function
Bits[2:7] Reserved
0=Default. Writing ‘1’ to the SLP_EN bit causes the
1=Writing ‘1’ to the SLP_EN bit does not cause the
0=Default. The WAK_STS bit is set on the high-to-low
1=The WAK_STS bit is set upon any enabled wakeup
system to sequence into the sleeping state
associated with the SLP_TYPx fields.
system to sequence into the sleeping state
associated with the SLP_TYPx fields; instead an SMI
is generated.
is set whenever ‘1’ is written to the SLP_EN bit; it is
enabled to generate an SMI through bit[0] of this
register.
transition of nPowerOn.
event and the high-to-low transition of nPowerOn.
198
DEFINITION
STATE
C
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