ENC28J60T/SO Microchip Technology, ENC28J60T/SO Datasheet - Page 16

• Manufacturer Part Number: ENC28J60T/SO
• Description: IC ETHERNET CTRLR W/SPI 28SOIC
• Manufacturer: Microchip Technology

Specifications of ENC28J60T/SO

• Controller Type: Ethernet Controller, MAC/10Base-T
• Interface: SPI
• Voltage - Supply: 3.1 V ~ 3.6 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• For Use With: DM163024 - BOARD DEMO PICDEM.NET 2AC164123 - BOARD DAUGHTER ETH PICTAIL PLUSAC164121 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ENC28J60
TABLE 3-2:
DS39662C-page 14
EPMCSL
EPMCSH
EPMOL
EPMOH
ERXFCON
EPKTCNT
MACON1
MACON3
MACON4
MABBIPG
MAIPGL
MAIPGH
MACLCON1
MACLCON2
MAMXFLL
MAMXFLH
MICMD
MIREGADR
MIWRL
MIWRH
MIRDL
MIRDH
MAADR5
MAADR6
MAADR3
MAADR4
MAADR1
MAADR2
EBSTSD
EBSTCON
EBSTCSL
EBSTCSH
MISTAT
EREVID
ECOCON
EFLOCON
EPAUSL
EPAUSH
Legend:
Note
Register Name
1:
2:
3:
(2)
(3)
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify.
CLKRDY resets to ‘0’ on Power-on Reset but is unaffected on all other Resets.
EREVID is a read-only register.
ECOCON resets to ‘---- -100’ on Power-on Reset and ‘---- -uuu’ on all other Resets.
Pattern Match Checksum Low Byte (EPMCS<7:0>)
Pattern Match Checksum High Byte (EPMCS<15:0>)
Pattern Match Offset Low Byte (EPMO<7:0>)
Ethernet Packet Count
Maximum Frame Length Low Byte (MAMXFL<7:0>)
Maximum Frame Length High Byte (MAMXFL<15:8>)
MII Write Data Low Byte (MIWR<7:0>)
MII Write Data High Byte (MIWR<15:8>)
MII Read Data Low Byte (MIRD<7:0>)
MII Read Data High Byte(MIRD<15:8>)
MAC Address Byte 5 (MAADR<15:8>)
MAC Address Byte 6 (MAADR<7:0>)
MAC Address Byte 3 (MAADR<31:24>), OUI Byte 3
MAC Address Byte 4 (MAADR<23:16>)
MAC Address Byte 1 (MAADR<47:40>), OUI Byte 1
MAC Address Byte 2 (MAADR<39:32>), OUI Byte 2
Built-in Self-Test Fill Seed (EBSTSD<7:0>)
Built-in Self-Test Checksum Low Byte (EBSTCS<7:0>)
Built-in Self-Test Checksum High Byte (EBSTCS<15:8>)
Pause Timer Value Low Byte (EPAUS<7:0>)
Pause Timer Value High Byte (EPAUS<15:8>)
PADCFG2
UCEN
PSV2
Bit 7
ENC28J60 CONTROL REGISTER SUMMARY (CONTINUED)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Back-to-Back Inter-Packet Gap (BBIPG<6:0>)
Non-Back-to-Back Inter-Packet Gap Low Byte (MAIPGL<6:0>)
Non-Back-to-Back Inter-Packet Gap High Byte (MAIPGH<6:0>)
PADCFG1
ANDOR
DEFER
PSV1
Bit 6
—
—
—
—
—
—
—
—
—
—
Collision Window (COLWIN<5:0>)
PADCFG0
CRCEN
BPEN
PSV0
Bit 5
—
—
—
—
—
—
—
—
—
Pattern Match Offset High Byte (EPMO<12:8>)
MII Register Address (MIREGADR<4:0>)
Ethernet Revision ID (EREVID<4:0>)
NOBKOFF
TXCRCEN
PMEN
PSEL
Bit 4
Preliminary
—
—
—
—
—
r
Retransmission Maximum (RETMAX<3:0>)
PHDREN
TXPAUS
TMSEL1
MPEN
Bit 3
—
—
—
—
r
FULDPXS
HFRMEN
COCON2
RXPAUS
TMSEL0
NVALID
HTEN
Bit 2
—
—
FRMLNEN
PASSALL
COCON1
MIISCAN
FCEN1
MCEN
SCAN
Bit 1
TME
r
© 2008 Microchip Technology Inc.
MARXEN
COCON0
FULDPX
BISTST
FCEN0
BCEN
MIIRD
BUSY
Bit 0
r
0000 0000
0000 0000
0000 0000
---0 0000
1010 0001
0000 0000
---0 0000
0000 0000
-000 --00
-000 0000
-000 0000
-000 0000
---- 1111
--11 0111
0000 0000
0000 0110
---- --00
---0 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
---- 0000
---q qqqq
---- -100
---- -000
0000 0000
0001 0000
Reset
Value
on
Details
Page
on
51
51
51
51
48
43
34
35
36
36
34
34
34
34
34
34
21
19
19
19
19
19
34
34
34
34
34
34
76
75
76
76
21
22
56
57
57
6