ENC28J60T/SO Microchip Technology, ENC28J60T/SO Datasheet - Page 77

• Manufacturer Part Number: ENC28J60T/SO
• Description: IC ETHERNET CTRLR W/SPI 28SOIC
• Manufacturer: Microchip Technology

Specifications of ENC28J60T/SO

• Controller Type: Ethernet Controller, MAC/10Base-T
• Interface: SPI
• Voltage - Supply: 3.1 V ~ 3.6 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• For Use With: DM163024 - BOARD DEMO PICDEM.NET 2AC164123 - BOARD DAUGHTER ETH PICTAIL PLUSAC164121 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.0
The ENC28J60 features a Built-in Self-Test (BIST)
module which is designed to confirm proper operation
of each bit in the 8-Kbyte memory buffer. Although it is
primarily useful for testing during manufacturing, it
remains present and available for diagnostic purposes
by the user. The controller writes to all locations in the
buffer memory and requires several pieces of hardware
shared by normal Ethernet operations. Thus, the BIST
should only be used on Reset or after necessary
hardware is freed. When the BIST is used, the ECON1
register’s DMAST, RXEN and TXRTS bits should all be
clear.
REGISTER 15-1:
© 2008 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
bit 4
bit 3-2
bit 1
bit 0
R/W-0
PSV2
BUILT-IN SELF-TEST
CONTROLLER
PSV2:PSV0: Pattern Shift Value bits
When TMSEL<1:0> = 10:
The bits in EBSTSD will shift left by this amount after writing to each memory location.
When TMSEL<1:0> = 00, 01 or 11:
This value is ignored.
PSEL: Port Select bit
1 = DMA and BIST modules will swap ports when accessing the memory
0 = Normal configuration
TMSEL1:TMSEL0: Test Mode Select bits
11 = Reserved
10 = Pattern shift fill
01 = Address fill
00 = Random data fill
TME: Test Mode Enable bit
1 = Enable Test mode
0 = Disable Test mode
BISTST: Built-in Self-Test Start/Busy bit
1 = Test in progress; cleared automatically when test is done
0 = No test running
R/W-0
PSV1
EBSTCON: ETHERNET SELF-TEST CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
R/W-0
PSV0
R/W-0
PSEL
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TMSEL1
R/W-0
The BIST controller is operated through four registers:
• EBSTCON register (control and status register)
• EBSTSD register (fill seed/initial shift value)
• EBSTCSH and EBSTCSL registers (high and low
The EBSTCON register (Register 15-1) controls the
module’s overall operation, selecting the Testing
modes and starting the self-test process. The bit pat-
tern for memory tests is provided by the EBSTSD seed
register; its content is either used directly, or as the
seed for a
depending on the Test mode.
bytes of generated checksum)
TMSEL0
R/W-0
pseudo-random number
x = Bit is unknown
ENC28J60
R/W-0
TME
DS39662C-page 75
BISTST
R/W-0
generator,
bit 0