ENC28J60T/SO Microchip Technology, ENC28J60T/SO Datasheet - Page 96

• Manufacturer Part Number: ENC28J60T/SO
• Description: IC ETHERNET CTRLR W/SPI 28SOIC
• Manufacturer: Microchip Technology

Specifications of ENC28J60T/SO

• Controller Type: Ethernet Controller, MAC/10Base-T
• Interface: SPI
• Voltage - Supply: 3.1 V ~ 3.6 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• For Use With: DM163024 - BOARD DEMO PICDEM.NET 2AC164123 - BOARD DAUGHTER ETH PICTAIL PLUSAC164121 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ENC28J60
PHY Registers..................................................................... 19
Pinout Diagrams.................................................................... 1
Pinout I/O Descriptions ......................................................... 4
Power-Down........................................................................ 73
Power-on Reset (POR) ....................................................... 60
R
Read Control Register (RCR) ............................................. 27
Reader Response ............................................................... 92
Reading and Writing to the Buffer ....................................... 17
Receive Buffer..................................................................... 17
Receive Filters .................................................................... 47
Receiving Packets............................................................... 43
Registers
Reset................................................................................... 59
Revision History .................................................................. 89
DS39662C-page 94
Reading....................................................................... 19
Scanning ..................................................................... 19
Writing ......................................................................... 19
Associated Registers .................................................. 73
Broadcast Filter ........................................................... 52
Hash Table Filter......................................................... 52
Magic Packet Filter ..................................................... 52
Multicast Filter ............................................................. 52
Pattern Match Filter..................................................... 51
Unicast Filter ............................................................... 51
Associated Registers .................................................. 46
Calculating Buffer Free Space .................................... 45
Calculating Free Receive Buffer Space ...................... 45
Calculating Random Access Address ......................... 44
Freeing Buffer Space .................................................. 45
Reading....................................................................... 44
Status Vectors............................................................. 44
EBSTCON (Ethernet Self-Test Control)...................... 75
ECOCON (Clock Output Control) ................................. 6
ECON1 (Ethernet Control 1) ....................................... 15
ECON2 (Ethernet Control 2) ....................................... 16
EFLOCON (Ethernet Flow Control) ............................ 56
EIE (Ethernet Interrupt Enable)................................... 65
EIR (Ethernet Interrupt Request, Flag) ....................... 66
ERXFCON (Ethernet Receive Filter Control) .............. 48
ESTAT (Ethernet Status) ............................................ 64
MABBIPG (MAC Back-to-Back
MACON1 (MAC Control 1).......................................... 34
MACON3 (MAC Control 3).......................................... 35
MACON4 (MAC Control 4).......................................... 36
MICMD (MII Command) .............................................. 21
MISTAT (MII Status) ................................................... 21
PHCON1 (PHY Control 1)........................................... 61
PHCON2 (PHY Control 2)........................................... 37
PHID (PHY Device ID) ................................................ 22
PHIE (PHY Interrupt Enable) ...................................... 67
PHIR (PHY Interrupt Request, Flag) ........................... 67
PHLCON (PHY Module LED Control) ........................... 9
PHSTAT1 (Physical Layer Status 1) ........................... 23
PHSTAT2 (Physical Layer Status 2) ........................... 24
MAC and PHY Subsystem Resets.............................. 61
Power-on Reset .......................................................... 60
Receive Only Reset .................................................... 60
System Reset.............................................................. 60
Transmit Only Reset ................................................... 60
Inter-Packet Gap)................................................ 36
Preliminary
S
Serial Peripheral Interface. See SPI ................................... 25
SPI
SPI.
T
Termination Requirement ..................................................... 7
Timing Diagrams
Transmit Buffer ................................................................... 17
Transmitting Packets .......................................................... 39
W
WWW, On-Line Support ....................................................... 2
Bit Field Clear Command............................................ 29
Bit Field Set Command............................................... 29
Instruction Set............................................................. 26
Overview..................................................................... 25
Read Buffer Memory Command ................................. 28
Read Control Register Command............................... 27
System Reset Command............................................ 30
Write Buffer Memory Command ................................. 29
Write Control Register Command............................... 28
CLKOUT Transition ...................................................... 6
Read Control Register Command
Read Control Register Command
SPI Input ............................................................... 25, 82
SPI Output ............................................................ 25, 82
System Reset Command Sequence........................... 30
Write Buffer Memory Command Sequence ................ 29
Write Control Register Command Sequence.............. 28
Associated Registers .................................................. 42
Status Vectors ............................................................ 41
(ETH Registers).................................................. 27
(MAC/MII Registers) ........................................... 27
© 2008 Microchip Technology Inc.