ENC28J60T/SO Microchip Technology, ENC28J60T/SO Datasheet - Page 63

• Manufacturer Part Number: ENC28J60T/SO
• Description: IC ETHERNET CTRLR W/SPI 28SOIC
• Manufacturer: Microchip Technology

Specifications of ENC28J60T/SO

• Controller Type: Ethernet Controller, MAC/10Base-T
• Interface: SPI
• Voltage - Supply: 3.1 V ~ 3.6 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• For Use With: DM163024 - BOARD DEMO PICDEM.NET 2AC164123 - BOARD DAUGHTER ETH PICTAIL PLUSAC164121 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.5
The PHY module may be reset by writing a ‘1’ to the
PRST bit in the PHCON1 register (Register 11-1). All
the PHY register contents will revert to their Reset
defaults.
REGISTER 11-1:
© 2008 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13-12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6-0
Note 1:
R/W-0
R/W-0
PRST
r
PHY Subsystem Reset
Reset values of the Duplex mode/status bits depend on the connection of the LED to the LEDB pin (see
Section 2.6 “LED Configuration” for additional details).
PRST: PHY Software Reset bit
1 = PHY is processing a Software Reset (automatically resets to ‘0’ when done)
0 = Normal operation
PLOOPBK: PHY Loopback bit
1 = All data transmitted will be returned to the MAC. The twisted-pair interface will be disabled.
0 = Normal operation
Unimplemented: Read as ‘0’
PPWRSV: PHY Power-Down bit
1 = PHY is shut down
0 = Normal operation
Reserved: Maintain as ‘0’
Unimplemented: Read as ‘0’
PDPXMD: PHY Duplex Mode bit
1 = PHY operates in Full-Duplex mode
0 = PHY operates in Half-Duplex mode
Reserved: Maintain as ‘0’
Unimplemented: Read as ‘0’
PLOOPBK
R/W-0
U-0
—
PHCON1: PHY CONTROL REGISTER 1
W = Writable bit
‘1’ = Bit is set
U-0
U-0
—
—
(1)
U-0
U-0
—
—
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PPWRSV
R/W-0
Unlike other Resets, the PHY cannot be removed from
Reset immediately after setting PRST. The PHY
requires a delay, after which the hardware automati-
cally clears the PRST bit. After a Reset is issued, the
host controller should poll PRST and wait for it to
become clear before using the PHY.
U-0
—
R/W-0
U-0
—
r
x = Bit is unknown
ENC28J60
U-0
U-0
—
—
DS39662C-page 61
PDPXMD
R/W-0
U-0
—
bit 8
bit 0
(1)