ENC28J60T/SO Microchip Technology, ENC28J60T/SO Datasheet - Page 17

IC ETHERNET CTRLR W/SPI 28SOIC

ENC28J60T/SO

Manufacturer Part Number
ENC28J60T/SO
Description
IC ETHERNET CTRLR W/SPI 28SOIC
Manufacturer
Microchip Technology
Datasheets

Specifications of ENC28J60T/SO

Controller Type
Ethernet Controller, MAC/10Base-T
Interface
SPI
Voltage - Supply
3.1 V ~ 3.6 V
Current - Supply
160mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-SOIC (7.5mm Width)
For Use With
DM163024 - BOARD DEMO PICDEM.NET 2AC164123 - BOARD DAUGHTER ETH PICTAIL PLUSAC164121 - BOARD DAUGHTER PICTAIL ETHERNET
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ENC28J60T/SO
Manufacturer:
TOSHIBA
Quantity:
3 844
3.1.1
The ECON1 register, shown in Register 3-1, is used to
control the main functions of the ENC28J60. Receive
enable, transmit request, DMA control and bank select
bits can all be found in ECON1.
REGISTER 3-1:
© 2008 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
TXRST
R/W-0
ECON1 REGISTER
TXRST: Transmit Logic Reset bit
1 = Transmit logic is held in Reset
0 = Normal operation
RXRST: Receive Logic Reset bit
1 = Receive logic is held in Reset
0 = Normal operations
DMAST: DMA Start and Busy Status bit
1 = DMA copy or checksum operation is in progress
0 = DMA hardware is Idle
CSUMEN: DMA Checksum Enable bit
1 = DMA hardware calculates checksums
0 = DMA hardware copies buffer memory
TXRTS: Transmit Request to Send bit
1 = The transmit logic is attempting to transmit a packet
0 = The transmit logic is Idle
RXEN: Receive Enable bit
1 = Packets which pass the current filter configuration will be written into the receive buffer
0 = All packets received will be ignored
BSEL1:BSEL0: Bank Select bits
11 = SPI accesses registers in Bank 3
10 = SPI accesses registers in Bank 2
01 = SPI accesses registers in Bank 1
00 = SPI accesses registers in Bank 0
RXRST
R/W-0
ECON1: ETHERNET CONTROL REGISTER 1
W = Writable bit
‘1’ = Bit is set
DMAST
R/W-0
CSUMEN
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TXRTS
R/W-0
R/W-0
RXEN
x = Bit is unknown
ENC28J60
BSEL1
R/W-0
DS39662C-page 15
BSEL0
R/W-0
bit 0

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