ISP1161ABD ST-Ericsson Inc, ISP1161ABD Datasheet - Page 70

• Manufacturer Part Number: ISP1161ABD
• Description: IC USB HOST/DEVICE CTRLR 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161ABD

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1165; ISP1161ABD,157

Philips Semiconductors
Table 44:
9397 750 13962
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcµPInterruptEnable register: bit allocation
reserved
R/W
R/W
15
0
7
0
10.4.5 HcµPInterruptEnable register (R/W: 25H/A5H)
ClkReady
Table 43:
The bits 6:0 in this register are the same as those in the HcµPInterrupt register. They
are used together with bit 0 of the HcHardwareConfiguration register to enable or
disable the bits in the HcµPInterrupt register.
At power-on, all bits in this register are masked with logic 0. This means no interrupt
request output on the interrupt pin INT1 can be generated.
When the bit is set to logic 1, the interrupt for the bit is not masked but enabled.
Code (Hex): 25 — read
Code (Hex): A5 — write
Table 45:
Bit
1
0
Bit
15 to 7
6
R/W
R/W
14
0
6
0
HcµPInterrupt register: bit description
HcµPInterruptEnable register: bit description
Suspended
Symbol
ATLInt
SOFITLInt
Symbol
-
ClkReady
Enable
R/W
R/W
HC
13
0
5
0
Rev. 03 — 23 December 2004
Description
0 — no event
1 — implies that the microprocessor must read ATL data from the
HC. This requires that the HcBufferStatus register must first be
read. The time for this interrupt depends on the number of clocks
bit set for USB activities in each ms.
0 — no event
1 — implies that SOF indicates the 1 ms mark. The ITL buffer that
the HC has handled must be read. To know the ITL buffer status,
the HcBufferStatus register must first be read. This is for the
microprocessor to get ISO data to or from the HC. For more
information, see the 6th paragraph in
Description
reserved
0 — power-up value
1 — enables Clkready interrupt
Interrupt
Enable
OPR
Full-speed USB single-chip host and device controller
R/W
R/W
12
0
4
0
reserved
reserved
R/W
R/W
11
0
3
0
…continued
Interrupt
Enable
EOT
R/W
R/W
10
0
2
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Section
Interrupt
Enable
ISP1161A
R/W
R/W
ATL
9.5.
9
0
1
0
Interrupt
Enable
SOF
R/W
R/W
69 of 134
8
0
0
0