ISP1161ABD ST-Ericsson Inc, ISP1161ABD Datasheet - Page 76

• Manufacturer Part Number: ISP1161ABD
• Description: IC USB HOST/DEVICE CTRLR 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161ABD

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1165; ISP1161ABD,157

Philips Semiconductors
Table 62:
Table 64:
9397 750 13962
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcITLBufferPort register: bit allocation
HcATLBufferPort register: bit allocation
R/W
R/W
R/W
15
15
0
7
0
0
10.6.6 HcITLBufferPort register (R/W: 40H/C0H)
10.6.7 HcATLBufferPort register (R/W: 41H/C1H)
This is the ITL buffer RAM read/write port. The bits 15:8 contain the data byte that
comes from the ITL buffer RAM’s even address. The bits 7:0 contain the data byte
that comes from the ITL buffer RAM’s odd address.
Code (Hex): 40 — read
Code (Hex): C0 — write
Table 63:
The HCD must set the byte count into the HcTransferCounter register and check the
HcBufferStatus register before reading from or writing to the buffer. The HCD must
write the command (40H for read, C0H for write) once only, and then read or write
both bytes of the data word. After every read/write, the pointer of ITL buffer RAM will
be automatically increased by two to point to the next data word until it reaches the
value of HcTransferCounter register; otherwise, an internal EOT signal is not
generated to set the bit 2 (AllEOTInterrupt) of the HcµPInterrupt register and update
the HcBufferStatus register.
The HCD must take care of the fact that the internal buffer RAM is organized in bytes.
The HCD must write the byte count into the HcTransferCounter register, but the HCD
reads or writes the buffer RAM by 16 bits (by 1 data word).
This is the ATL buffer RAM read/write port. The bits 15:8 contain the data byte that
comes from the Acknowledged Transfer List (ATL) buffer RAM’s odd address. Bits 7:0
contain the data byte that comes from the ATL buffer RAM’s even address.
Code (Hex): 41 — read
Code (Hex): C1 — write
Bit
15 to 0
R/W
R/W
R/W
14
14
0
6
0
0
Symbol
DataWord[15:0]
HcITLBufferPort register: bit description
R/W
R/W
R/W
13
13
0
5
0
0
Rev. 03 — 23 December 2004
Full-speed USB single-chip host and device controller
R/W
R/W
R/W
12
12
DataWord[15:8]
DataWord[15:8]
0
4
0
0
DataWord[7:0]
Description
read/write ITL buffer RAM’s two data bytes.
R/W
R/W
R/W
11
11
0
3
0
0
R/W
R/W
R/W
10
10
0
2
0
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ISP1161A
R/W
R/W
R/W
9
0
1
0
9
0
R/W
R/W
R/W
75 of 134
8
0
0
0
8
0