RC82562EP Intel, RC82562EP Datasheet - Page 55

• Manufacturer Part Number: RC82562EP
• Description: IC ETH 10/100 PLC DEV CTRL 64BGA
• Manufacturer: Intel

Specifications of RC82562EP

• Rohs Status: RoHS non-compliant
• Controller Type: Ethernet Controller
• Interface: IEEE 802.3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Current - Supply: -
• Operating Temperature: -
• Other names: 832361

6.3.4.3
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Note: Since the address field is written most significant bit first, software must know the address field
Software Read Access from the EEPROM
To read from the EEPROM, software is required to perform the following steps. The example is a
read from address 02h (0000 0010b).
size prior to starting a read or write access.
4. Read a 16-bit word from the EEPROM one bit at a time, starting with the most significant bit,
1. Activate the EEPROM by writing a 1 to the EECS bit.
2. Write the read opcode, including the start bit (110b), one bit at a time, starting with the most
3. Write the address field, one bit at a time, starting with the most significant bit.
4. Read a 16-bit word from the EEPROM, one bit at a time, starting with the most significant bit.
5. De-activate the EEPROM by writing a 0 to the EECS bit.
to complete the transaction (but discard the output).
significant bit (1):
e. Repeat steps 3.a through 3.d until the EEDO bit equals 0. The number of loop iterations
a. Write a 1 to the EESK bit then wait the minimum SK high time.
b. Read a data bit from the EEDO bit.
c. Write a 0 to the EESK bit then wait the minimum SK low time.
d. Repeat steps 4.a through 4.c an additional 15 times.
e. De-activate the EEPROM by writing a 0 to the EECS bit.
a. Write the opcode bit to the EEDI bit.
b. Write a 1 to EESK bit then wait the minimum SK high time.
c. Write a 0 to EESK bit then wait the minimum SK low time.
d. Repeat steps 2.a through 2.c for the next two opcode bits.
a. Write the address bit to the EEDI bit.
b. Write a 1 to EESK bit then wait the minimum SK high time.
c. Write a 0 to EESK bit then wait the minimum SK low time.
d. Read the EEDO bit (looking for the dummy 0 bit).
e. Repeat steps 3.a through 3.d until the EEDO bit equals 0, indicating that the address field
a. Write a 1 to the EESK bit then wait the minimum SK high time.
b. Read a data bit from the EEDO bit.
c. Write a 0 to the EESK bit then wait the minimum SK low time.
d. Repeat steps 4.a through 4.d an additional 15 times.
performed is the number of bits in the address field.
has been completely written.
Host Software Interface
47