DSPIC30F3011-30I/PT Microchip Technology Inc., DSPIC30F3011-30I/PT Datasheet - Page 238

• Manufacturer Part Number: DSPIC30F3011-30I/PT
• Description: 16 BIT MCU/DSP 44LD 30MIPS 24 KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F3011-30I/PT

• A/d Inputs: 9-Channels, 10-Bit
• Cpu Speed: 30 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 30
• Interface: I2C/SPI/UART, USART
• Ios: 30
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 44-pin TQFP
• Programmable Memory: 24K Bytes
• Ram Size: 1K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

dsPIC30F
PORTA Register Map ......................................................... 69
PORTB Register Map ......................................................... 69
PORTC Register Map ......................................................... 69
PORTD Register Map ......................................................... 69
PORTE Register Map ......................................................... 69
PORTF Register Map.......................................................... 70
PORTG Register Map ......................................................... 70
Position Measurement Mode .............................................. 96
Power Saving Modes ........................................................ 161
Power Saving Modes (Sleep and Idle).............................. 151
Power-Down Current (I
Power-on Reset (POR) ..................................................... 151
Power-up Timer
PRO MATE II Universal Device Programmer ................... 175
Product Identification System............................................ 241
Program Address Space ..................................................... 31
Program and EEPROM Characteristics ............................ 191
Program Counter................................................................. 20
Program Data Table Access ............................................... 33
Program Space Visibility
Program Space Visibility from Data Space ......................... 33
Programmable................................................................... 151
Programmable Digital Noise Filters..................................... 97
Programmer’s Model........................................................... 20
Programming Operations .................................................... 58
Programming, Device Instructions .................................... 165
Protection Against Accidental Writes to OSCCON ........... 156
PWM Duty Cycle Comparison Units ................................. 106
PWM FAULT Pins ............................................................. 108
PWM Operation During CPU Idle Mode............................ 109
PWM Operation During CPU Sleep Mode ........................ 109
PWM Output and Polarity Control ..................................... 108
PWM Output Override....................................................... 108
PWM Period ...................................................................... 105
DS70082G-page 236
Idle ............................................................................ 162
Sleep......................................................................... 161
Oscillator Start-up Timer (OST) ................................ 151
Power-up Timer (PWRT) .......................................... 151
Timing Characteristics .............................................. 196
Timing Requirements ................................................ 197
Alignment and Data Access Using Table Instructions 32
Construction ................................................................ 31
Data Access from, Address Generation...................... 31
Memory Map ............................................................... 35
Table Instructions
Window into Program Space Operation...................... 34
Diagram ...................................................................... 21
Algorithm for Program Flash ....................................... 58
Erasing a Row of Program Memory ............................ 59
Initiating the Programming Sequence ......................... 61
Loading Write Latches ................................................ 60
Duty Cycle Register Buffers ...................................... 106
Enable Bits................................................................ 108
FAULTStates ............................................................ 108
Modes ....................................................................... 109
Priority ....................................................................... 109
Output Pin Control .................................................... 108
Complementary Output Mode ................................... 108
Synchronization ........................................................ 108
TBLRDH.............................................................. 32
TBLRDL .............................................................. 32
TBLWTH ............................................................. 32
TBLWTL.............................................................. 32
Cycle-by-Cycle.................................................. 109
Latched ............................................................. 109
PD
) ................................................ 186
Preliminary
PWM Special Event Trigger.............................................. 109
PWM Time Base............................................................... 104
PWM Update Lockout....................................................... 109
Q
QEA/QEB Input Characteristics........................................ 204
QEI Module
Quadrature Decoder Timing Requirements...................... 204
Quadrature Encoder Interface (QEI) Module...................... 95
Quadrature Encoder Interface Interrupts ............................ 98
Quadrature Encoder Interface Logic................................... 96
R
Reset ........................................................................ 151, 157
Reset Sequence ................................................................. 53
Reset Timing Characteristics............................................ 196
Reset Timing Requirements ............................................. 197
Resets
RTSP Operation ................................................................. 58
S
Serial Peripheral Interface. See SPI
Simple Capture Event Mode
Simple OC/PWM Mode Timing Requirements ................. 202
Simple Output Compare Match Mode ................................ 92
Simple PWM Mode ............................................................. 92
Single Pulse PWM Operation ........................................... 108
Software Simulator (MPLAB SIM) .................................... 174
Software Simulator (MPLAB SIM30) ................................ 174
Software Stack Pointer, Frame Pointer .............................. 20
SPI .................................................................................... 111
SPI Mode
SPI Module ....................................................................... 111
Postscaler ................................................................. 109
Continuous Up/Down Counting Modes..................... 104
Double Update Mode................................................ 104
Free Running Mode .................................................. 104
Postscaler ................................................................. 105
Prescaler .................................................................. 105
Single Shot Mode ..................................................... 104
External Clock Timing Requirements ....................... 200
Index Pulse Timing Characteristics .......................... 205
Index Pulse Timing Requirements............................ 205
Operation During CPU Idle Mode ............................... 97
Operation During CPU Sleep Mode............................ 97
Register Map .............................................................. 99
Timer Operation During CPU Idle Mode..................... 98
Timer Operation During CPU Sleep Mode ................. 97
Reset Sources ............................................................ 53
BOR, Programmable ................................................ 159
POR .......................................................................... 157
POR with Long Crystal Start-up Time....................... 159
Capture Buffer Operation............................................ 88
Capture Prescaler....................................................... 88
Hall Sensor Mode ....................................................... 88
Input Capture in CPU Idle Mode................................. 89
Timer2 and Timer3 Selection Mode............................ 88
Input Pin Fault Protection ........................................... 92
Period ......................................................................... 93
CALL Stack Frame ..................................................... 37
Slave Select Synchronization ................................... 113
SPI1 Register Map.................................................... 114
SPI2 Register Map.................................................... 114
Framed SPI Support ................................................. 113
Operating Function Description ................................ 111
Operating without FSCM and PWRT................ 159
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