DSPIC30F3011-30I/PT Microchip Technology Inc., DSPIC30F3011-30I/PT Datasheet - Page 82

• Manufacturer Part Number: DSPIC30F3011-30I/PT
• Description: 16 BIT MCU/DSP 44LD 30MIPS 24 KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F3011-30I/PT

• A/d Inputs: 9-Channels, 10-Bit
• Cpu Speed: 30 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 30
• Interface: I2C/SPI/UART, USART
• Ios: 30
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 44-pin TQFP
• Programmable Memory: 24K Bytes
• Ram Size: 1K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

dsPIC30F
10.1
The 32-bit timer can be placed in the Gated Time Accu-
mulation mode. This mode allows the internal T
increment the respective timer when the gate input sig-
nal (T2CK pin) is asserted high. Control bit TGATE
(T2CON<6>) must be set to enable this mode. When in
this mode, Timer2 is the originating clock source. The
TGATE setting is ignored for Timer3. The timer must be
enabled (TON = 1) and the timer clock source set to
internal (TCS = 0).
The falling edge of the external signal terminates the
count operation, but does not reset the timer. The user
must reset the timer in order to start counting from zero.
10.2
When a match occurs between the 32-bit timer (TMR3/
TMR2) and the 32-bit combined period register (PR3/
PR2) or between the 16-bit timer (TMR3) and the 16-bit
period register (PR3), a special ADC trigger event
signal is generated by Timer3.
10.3
The input clock (F
has a prescale option of 1:1, 1:8, 1:64, and 1:256
selected by control bits TCKPS<1:0> (T2CON<5:4>
and T3CON<5:4>). For the 32-bit timer operation, the
originating clock source is Timer2. The prescaler oper-
ation for Timer3 is not applicable in this mode. The
prescaler counter is cleared when any of the following
occurs:
• a write to the TMR2/TMR3 register
• clearing either of the TON (T2CON<15> or
• device Reset such as POR and BOR
However, if the timer is disabled (TON = 0), then the
Timer 2 prescaler cannot be reset, since the prescaler
clock is halted.
TMR2/TMR3 is not cleared when T2CON/T3CON is
written.
DS70082G-page 80
T3CON<15>) bits to ‘0’
Timer Gate Operation
ADC Event Trigger
Timer Prescaler
OSC
/4 or external clock) to the timer
CY
Preliminary
to
10.4
During CPU Sleep mode, the timer will not operate,
because the internal clocks are disabled.
10.5
The 32-bit timer module can generate an interrupt on
period match, or on the falling edge of the external gate
signal. When the 32-bit timer count matches the
respective 32-bit period register, or the falling edge of
the external “gate” signal is detected, the T3IF bit
(IFS0<7>) is asserted and an interrupt will be gener-
ated if enabled. In this mode, the T3IF interrupt flag is
used as the source of the interrupt. The T3IF bit must
be cleared in software.
Enabling an interrupt is accomplished via the
respective timer interrupt enable bit, T3IE (IEC0<7>)..
Note:
Timer Operation During Sleep
Mode
Timer Interrupt
In some devices, one or more of the TxCK
pins may be absent. For these timers
without the external clock input pin, the
following modes should not be used:
1. TCS = 1 (16-bit counter)
2. TCS = 0, TGATE = 1 (gated time
accumulation.
 2004 Microchip Technology Inc.