DSPIC30F3011-30I/PT Microchip Technology Inc., DSPIC30F3011-30I/PT Datasheet - Page 70

• Manufacturer Part Number: DSPIC30F3011-30I/PT
• Description: 16 BIT MCU/DSP 44LD 30MIPS 24 KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F3011-30I/PT

• A/d Inputs: 9-Channels, 10-Bit
• Cpu Speed: 30 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 30
• Interface: I2C/SPI/UART, USART
• Ios: 30
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 44-pin TQFP
• Programmable Memory: 24K Bytes
• Ram Size: 1K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

dsPIC30F
A parallel I/O (PIO) port that shares a pin with a periph-
eral is, in general, subservient to the peripheral. The
peripheral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pad cell. Figure 8-2 shows how ports are shared
with other peripherals, and the associated I/O cell (pad)
to which they are connected. Table 8-2 through
Table 8-7 show the formats of the registers for the
shared ports, PORTB through PORTG.
8.2
The use of the ADPCFG and TRIS registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their correspond-
ing TRIS bit set (input). If the TRIS bit is cleared (out-
put), the digital output level (V
converted.
FIGURE 8-2:
DS70082G-page 68
Note:
Configuring Analog Port Pins
The actual bits in use vary between
devices.
Data Bus
WR TRIS
WR LAT +
WR Port
BLOCK DIAGRAM OF A SHARED PORT STRUCTURE
Read Port
Peripheral Output Enable
Peripheral Output Data
Peripheral Input Data
Peripheral Module Enable
PIO Module
Peripheral Module
Read TRIS
OH
Read LAT
or V
TRIS Latch
Data Latch
D
D
CK
CK
OL
) will be
Q
Q
Preliminary
When reading the PORT register, all pins configured as
analog input channel will read as cleared (a low level).
Pins configured as digital inputs will not convert an ana-
log input. Analog levels on any pin that is defined as a
digital input (including the ANx pins), may cause the
input buffer to consume current that exceeds the
device specifications.
8.2.1
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically this instruction
would be a NOP.
EXAMPLE 8-1:
MOV
MOV
NOP
btss
1
1
0xFF00, W0
W0, TRISBB
PORTB, #13
0
0
Output Data
Output Enable
I/O PORT WRITE/READ TIMING
Output Multiplexers
Input Data
I/O Cell
; Configure PORTB<15:8>
; as inputs
; and PORTB<7:0> as outputs
; Delay 1 cycle
; Next Instruction
PORT WRITE/READ
EXAMPLE
 2004 Microchip Technology Inc.
I/O Pad