DSPIC30F3011-30I/PT Microchip Technology Inc., DSPIC30F3011-30I/PT Datasheet - Page 91
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DSPIC30F3011-30I/PT
Manufacturer Part Number
DSPIC30F3011-30I/PT
Description
16 BIT MCU/DSP 44LD 30MIPS 24 KB FLASH
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC30F3011-30IPT.pdf
(244 pages)
Specifications of DSPIC30F3011-30I/PT
A/d Inputs
9-Channels, 10-Bit
Cpu Speed
30 MIPS
Eeprom Memory
1K Bytes
Input Output
30
Interface
I2C/SPI/UART, USART
Ios
30
Memory Type
Flash
Number Of Bits
16
Package Type
44-pin TQFP
Programmable Memory
24K Bytes
Ram Size
1K Bytes
Timers
5-16-bit, 2-32-bit
Voltage, Range
2.5-5.5
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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12.2
An input capture event will generate a device wake-up
or interrupt, if enabled, if the device is in CPU Idle or
Sleep mode.
Independent of the timer being enabled, the input
capture module will wake-up from the CPU Sleep or
Idle mode when a capture event occurs, if ICM<2:0> =
111 and the interrupt enable bit is asserted. The same
wake-up can generate an interrupt, if the conditions for
processing the interrupt have been satisfied. The
wake-up feature is useful as a method of adding extra
external pin interrupts.
12.2.1
CPU Sleep mode allows input capture module opera-
tion with reduced functionality. In the CPU Sleep
mode, the ICI<1:0> bits are not applicable, and the
input capture module can only function as an external
interrupt source.
The capture module must be configured for interrupt
only on the rising edge (ICM<2:0> = 111), in order for
the input capture module to be used while the device
is in Sleep mode. The prescale settings of 4:1 or 16:1
are not applicable in this mode.
2004 Microchip Technology Inc.
Input Capture Operation During
Sleep and Idle Modes
INPUT CAPTURE IN CPU SLEEP
MODE
Preliminary
12.2.2
CPU Idle mode allows input capture module operation
with full functionality. In the CPU Idle mode, the interrupt
mode selected by the ICI<1:0> bits are applicable, as
well as the 4:1 and 16:1 capture prescale settings,
which are defined by control bits ICM<2:0>. This mode
requires the selected timer to be enabled. Moreover, the
ICSIDL bit must be asserted to a logic ‘0’.
If the input capture module is defined as ICM<2:0> =
111 in CPU Idle mode, the input capture pin will serve
only as an external interrupt pin.
12.3
The input capture channels have the ability to generate
an interrupt, based upon the selected number of cap-
ture events. The selection number is set by control bits
ICI<1:0> (ICxCON<6:5>).
Each channel provides an interrupt flag (ICxIF) bit. The
respective capture channel interrupt flag is located in
the corresponding IFSx Status register.
Enabling an interrupt is accomplished via the respec-
tive capture channel interrupt enable (ICxIE) bit. The
capture interrupt enable bit is located in the
corresponding IEC Control register.
Input Capture Interrupts
INPUT CAPTURE IN CPU IDLE
MODE
dsPIC30F
DS70082G-page 89
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