FIN1048MX Fairchild Semiconductor, FIN1048MX Datasheet
FIN1048MX
Specifications of FIN1048MX
FIN1048MX_NL
FIN1048MX_NLTR
FIN1048MX_NLTR
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FIN1048MX Summary of contents
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... Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram © 2003 Fairchild Semiconductor Corporation Features Greater than 400Mbs data rate Flow-through pinout simplifies PCB layout 3 ...
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Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Input Voltage (V ) OUT DC Output Current ( Storage Temperature Range (T ) STG Max Junction Temperature ( Lead Temperature ...
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AC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified Symbol Parameter t Propagation Delay LOW-to-HIGH PLH t Propagation Delay HIGH-to-LOW PHL t Output Rise Time (20% to 80%) TLH t Output Fall Time (80% to 20%) ...
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FIGURE 2. LVDS Input to LVTTL Output AC Waveforms Voltage Waveforms Enable and Disable Times FIGURE 3. LVTTL Outputs Test Circuit and AC Waveforms www.fairchildsemi.com Test Circuit for LVTTL Outputs 4 ...
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Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 5 www.fairchildsemi.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...