PIC18F4550-I/PT Microchip Technology Inc., PIC18F4550-I/PT Datasheet - Page 189

• Manufacturer Part Number: PIC18F4550-I/PT
• Description: 44 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4550-I/PT

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 34
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

18.0
PIC18F4455/4550 USB devices provide a Streaming
Parallel Port as a high-speed interface for moving data
to and from an external system. This parallel port
operates as a master port, complete with chip select
and clock outputs to control the movement of data to
slave devices. Data can be channelled either directly to
the USB SIE or to the microprocessor core. Figure 18-1
shows a block view of the SPP data path.
FIGURE 18-1:
REGISTER 18-1:
© 2006 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-2
bit 1
bit 0
Note:
USB
SIE
CPU
U-0
—
STREAMING PARALLEL PORT
The Streaming Parallel Port is only
available on 40/44-pin devices.
Unimplemented: Read as ‘0’
SPPOWN: SPP Ownership bit
1 = USB peripheral controls the SPP
0 = Microcontroller directly controls the SPP
SPPEN: SPP Enable bit
1 = SPP is enabled
0 = SPP is disabled
PIC18F4455/4550
U-0
—
SPP DATA PATH
SPPCON: SPP CONTROL REGISTER
Logic
SPP
W = Writable bit
‘1’ = Bit is set
U-0
—
CK1SPP
CK2SPP
OESPP
CSSPP
SPP<7:0>
PIC18F2455/2550/4455/4550
U-0
Preliminary
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
In addition, the SPP can provide time multiplexed
addressing information along with the data by using the
second strobe output. Thus, the USB endpoint number
can be written in conjunction with the data for that
endpoint.
18.1
The operation of the SPP is controlled by two registers:
SPPCON and SPPCFG. The SPPCON register
(Register 18-1) controls the overall operation of the
parallel port and determines if it operates under USB or
microcontroller
(Register 18-2) controls timing configuration and pin
outputs.
18.1.1
To enable the SPP, set the SPPEN bit (SPPCON<0>).
In addition, the TRIS bits for the corresponding SPP
pins must be properly configured. At a minimum:
• Bits TRISD<7:0> must be set (= 1)
• Bits TRISE<2:1> must be cleared (= 0)
If CK1SPP is to be used:
• Bit TRISE<0> must be cleared (= 0)
If CSPP is to be used:
• Bit TRISB<4> must be cleared (= 0)
U-0
—
SPP Configuration
ENABLING THE SPP
U-0
—
control.
x = Bit is unknown
SPPOWN
The
R/W-0
SPPCFG
DS39632C-page 187
SPPEN
R/W-0
register
bit 0