PIC18F4550-I/PT Microchip Technology Inc., PIC18F4550-I/PT Datasheet - Page 237

• Manufacturer Part Number: PIC18F4550-I/PT
• Description: 44 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4550-I/PT

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 34
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

19.4.17.3
Bus collision occurs during a Stop condition if:
a)
b)
FIGURE 19-33:
FIGURE 19-34:
© 2006 Microchip Technology Inc.
After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
SDA
SCL
PEN
BCLIF
P
SSPIF
SDA
SCL
PEN
BCLIF
P
SSPIF
Bus Collision During a Stop
Condition
BUS COLLISION DURING A STOP CONDITION (CASE 1)
BUS COLLISION DURING A STOP CONDITION (CASE 2)
SDA asserted low
Assert SDA
T
BRG
T
BRG
PIC18F2455/2550/4455/4550
Preliminary
T
BRG
T
BRG
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD<6:0>
and counts down to ‘0’. After the BRG times out, SDA
is sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 19-33). If the SCL pin is
sampled low before SDA is allowed to float high, a bus
collision occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 19-34).
SCL goes low before SDA goes high,
set BCLIF
T
BRG
T
BRG
SDA sampled
low after T
set BCLIF
‘0’
‘0’
DS39632C-page 235
‘0’
‘0’
BRG
,