PIC18F4550-I/PT Microchip Technology Inc., PIC18F4550-I/PT Datasheet - Page 253

• Manufacturer Part Number: PIC18F4550-I/PT
• Description: 44 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4550-I/PT

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 34
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

FIGURE 20-6:
FIGURE 20-7:
TABLE 20-6:
© 2006 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
BAUDCON
SPBRGH
SPBRG
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1:
Name
Note:
RX (pin)
Rcv Shift Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word
causing the OERR (Overrun) bit to be set.
Reserved in 28-pin devices; always maintain these bits clear.
RX
BRG16
GIE/GIEH PEIE/GIEL
EUSART Receive Register
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
ABDOVF
SPPIE
SPPIP
SPPIF
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
(1)
(1)
(1)
EUSART RECEIVE BLOCK DIAGRAM
ASYNCHRONOUS RECEPTION, RXDTP = 0 (RX NOT INVERTED)
Start
bit
SPBRGH
Baud Rate Generator
x64 Baud Rate CLK
RXDTP
bit 0
RCIDL
and Control
ADIE
ADIP
ADIF
Pin Buffer
Bit 6
RX9
TX9
bit 1
SPBRG
SPEN
TMR0IE
RXDTP
SREN
TXEN
RCIE
RCIP
RCIF
Bit 5
PIC18F2455/2550/4455/4550
bit 7/8
Recovery
Preliminary
Interrupt
Data
TXCKP
Stop
INT0IE
CREN
SYNC
or
or
bit
64
16
TXIE
TXIP
4
Bit 4
TXIF
Word 1
RCREG
CREN
Start
bit
ADDEN
SENDB
bit 0
BRG16
SSPIE
SSPIP
SSPIF
RBIE
Bit 3
RX9
Stop
MSb
RCIF
RCIE
RX9D
TMR0IF
CCP1IF
CCP1IE
CCP1IP
bit 7/8
BRGH
Word 2
RCREG
FERR
(8)
Bit 2
—
OERR
7
Stop
bit
RSR Register
RCREG Register
TMR2IE
TMR2IP
TMR2IF
INT0IF
OERR
TRMT
8
Start
WUE
Bit 1
bit
Data Bus
1
FERR
0
TMR1IE
TMR1IP
TMR1IF
ABDEN
RX9D
TX9D
DS39632C-page 251
RBIF
bit 7/8
Bit 0
LSb
Start
FIFO
Stop
bit
on page
Values
Reset
51
54
54
54
53
53
53
53
53
53