PIC18F4550-I/PT Microchip Technology Inc., PIC18F4550-I/PT Datasheet - Page 350

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PIC18F4550-I/PT

Manufacturer Part Number
PIC18F4550-I/PT
Description
44 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F4550-I/PT

A/d Inputs
13-Channel, 10-Bit
Comparators
2
Cpu Speed
12 MIPS
Eeprom Memory
256 Bytes
Input Output
34
Interface
I2C/SPI/UART/USART/USB
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin TQFP
Programmable Memory
32K Bytes
Ram Size
2K Bytes
Speed
48 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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PIC18F2455/2550/4455/4550
XORWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39632C-page 348
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
W
REG
W
Q1
=
=
=
=
register ‘f’
Exclusive OR W with f
XORWF
0
d
a
(W) .XOR. (f)
N, Z
Exclusive OR the contents of W with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in the register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
XORWF
Read
0001
Q2
f
AFh
B5h
1Ah
B5h
[0,1]
[0,1]
255
REG, 1, 0
f {,d {,a}}
10da
Process
Data
dest
Q3
95 (5Fh). See
ffff
destination
Write to
Q4
ffff
Preliminary
© 2006 Microchip Technology Inc.

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