PIC18F87K22-I/PTRSL Microchip Technology Inc., PIC18F87K22-I/PTRSL Datasheet - Page 129

• Manufacturer Part Number: PIC18F87K22-I/PTRSL
• Description: 128kB Flash, 4kB RAM, 1kB EE, nanoWatt XLP, GP, 80 TQFP 12x12x1mm TRAY
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F87K22-I/PTRSL

• A/d Inputs: 24-Channel, 12-Bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 69
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 3.8K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 6-8-bit, 5-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

8.7
In 8-Bit Data Width mode, the external memory bus
operates only in Multiplexed mode; that is, data shares
the 8 Least Significant bits of the address bus.
Figure 8-6
mode for PIC18F8XK22 devices. This mode is used for
a single, 8-bit memory connected for 16-bit operation.
The instructions will be fetched as two 8-bit bytes on a
shared data/address bus. The two bytes are sequen-
tially fetched within one instruction cycle (T
Therefore, the designer must choose external memory
devices according to timing calculations based on
1/2 T
ory speed selection, glue logic propagation delay times
must be considered, along with setup and hold times.
The Address Latch Enable (ALE) pin indicates that the
address bits, AD<15:0>, are available on the external
memory interface bus. The Output Enable (OE) signal
FIGURE 8-6:
 2011 Microchip Technology Inc.
CY
(2 times the instruction rate). For proper mem-
8-Bit Data Width Mode
Note 1:
shows an example of 8-Bit Multiplexed
2:
PIC18F87K22
Upper order address bits are only used for 20-bit address width. The upper AD byte is used for all
address widths except 8-bit.
This signal only applies to table writes. See
AD<15:8>
A<19:16>
8-BIT MULTIPLEXED MODE EXAMPLE
AD<7:0>
WRL
ALE
BA0
CE
OE
(1)
(1)
CY
).
373
Section 7.1 “Table Reads and Table
PIC18F87K22 FAMILY
will enable one byte of program memory for a portion of
the instruction cycle, then BA0 will change and the
second byte will be enabled to form the 16-bit instruc-
tion word. The Least Significant bit of the address, BA0,
must be connected to the memory devices in this
mode. The Chip Enable (CE) signal is active at any
time that the microcontroller accesses external
memory, whether reading or writing. It is inactive
(asserted high) whenever the device is in Sleep mode.
This generally includes basic EPROM and Flash
devices. It allows table writes to byte-wide external
memories.
During a TBLWT instruction cycle, the TABLAT data is
presented on the upper and lower bytes of the
AD<15:0> bus. The appropriate level of the BA0 control
line is strobed on the LSb of the TBLPTR.
D<7:0>
A<19:0>
D<15:8>
Address Bus
Data Bus
Control Lines
A0
OE
A<x:1>
D<7:0>
CE
Writes”.
WR
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