PIC18F87K22-I/PTRSL Microchip Technology Inc., PIC18F87K22-I/PTRSL Datasheet - Page 543

• Manufacturer Part Number: PIC18F87K22-I/PTRSL
• Description: 128kB Flash, 4kB RAM, 1kB EE, nanoWatt XLP, GP, 80 TQFP 12x12x1mm TRAY
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F87K22-I/PTRSL

• A/d Inputs: 24-Channel, 12-Bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 69
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 3.8K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 6-8-bit, 5-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

 2011 Microchip Technology Inc.
Bus Collision During Start Condition (SCLx = 0) ...... 323
Bus Collision During Start Condition
Bus Collision During Stop Condition (Case 1) .......... 325
Bus Collision During Stop Condition (Case 2) .......... 325
Bus Collision for Transmit and Acknowledge............ 321
Capture/Compare/PWM............................................ 513
CLKO and I/O ........................................................... 505
Clock Synchronization .............................................. 307
Clock/Instruction Cycle ............................................... 92
EUSART Synchronous Transmission
EUSART/AUSART Synchronous
Example SPI Master Mode (CKE = 0) ...................... 514
Example SPI Master Mode (CKE = 1) ...................... 515
Example SPI Slave Mode (CKE = 0) ........................ 516
Example SPI Slave Mode (CKE = 1) ........................ 517
External Clock........................................................... 503
External Memory Bus for SLEEP (Extended
External Memory Bus for TBLRD (Extended
Fail-Safe Clock Monitor (FSCM) ............................... 425
First Start Bit Timing ................................................. 315
Full-Bridge PWM Output ........................................... 270
Half-Bridge PWM Output .................................. 268, 275
High-Voltage Detect Operation (VDIRMAG = 1)....... 383
HLVD Characteristics................................................ 511
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Low-Voltage Detect Operation (VDIRMAG = 0) ....... 382
MSSP I
MSSP I
Parallel Slave Port (PSP) Read ................................ 191
Parallel Slave Port (PSP) Write ................................ 190
Program Memory Fetch (8-bit).................................. 506
Program Memory Read............................................. 507
Program Memory Write............................................. 508
PWM Auto-Shutdown with Auto-Restart
PWM Auto-Shutdown with Firmware
PWM Direction Change ............................................ 271
PWM Direction Change at Near 100%
PWM Output ............................................................. 255
PWM Output (Active-High)........................................ 266
PWM Output (Active-Low) ........................................ 267
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C Acknowledge Sequence ..................................... 320
C Bus Data ............................................................. 519
C Bus Start/Stop Bits.............................................. 518
C Master Mode (7 or 10-Bit Transmission) ............ 318
C Master Mode (7-Bit Reception)........................... 319
C Slave Mode (10-Bit Reception, SEN = 0,
C Slave Mode (10-Bit Reception, SEN = 0) ........... 304
C Slave Mode (10-Bit Reception, SEN = 1) ........... 309
C Slave Mode (10-Bit Transmission)...................... 305
C Slave Mode (7-bit Reception, SEN = 0,
C Slave Mode (7-Bit Reception, SEN = 0) ............. 300
C Slave Mode (7-Bit Reception, SEN = 1) ............. 308
C Slave Mode (7-Bit Transmission)........................ 302
C Slave Mode General Call Address
C Stop Condition Receive or Transmit Mode ......... 320
(Master/Slave) .................................................. 522
Receive (Master/Slave) .................................... 522
Microcontroller Mode) ............................... 128, 130
Microcontroller Mode) ............................... 128, 130
ADMSK = 01001).............................................. 303
ADMSK = 01011).............................................. 301
Sequence (7 or 10-Bit Addressing Mode)......... 310
Enabled (PxRSEN = 1) ..................................... 274
Restart (PxRSEN = 0)....................................... 274
Duty Cycle ........................................................ 272
(SDAx Only) ..................................................... 322
2
2
C Bus Data.................................................. 520
C Bus Start/Stop Bits .................................. 520
PIC18F87K22 FAMILY
Timing Diagrams and Specifications
Repeated Start Condition ......................................... 316
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence............................. 344
Slave Synchronization .............................................. 287
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 286
SPI Mode (Slave Mode, CKE = 0) ............................ 288
SPI Mode (Slave Mode, CKE = 1) ............................ 288
Steering Event at Beginning of Instruction
Steering Event at End of Instruction
Synchronous Reception (Master Mode, SREN) ....... 347
Synchronous Transmission ...................................... 345
Synchronous Transmission (Through TXEN) ........... 346
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer Pulse Generation............................................ 242
Timer0 and Timer1 External Clock ........................... 512
Timer1 Gate Count Enable Mode............................. 204
Timer1 Gate Single Pulse Mode............................... 206
Timer1 Gate Single Pulse/Toggle
Timer1 Gate Toggle Mode........................................ 205
Timer3/5/7 Gate Count Enable Mode....................... 217
Timer3/5/7 Gate Single Pulse Mode......................... 219
Timer3/5/7 Gate Single Pulse/Toggle
Timer3/5/7 Gate Toggle Mode.................................. 218
Transition for Entry to Idle Mode ................................ 63
Transition for Entry to SEC_RUN Mode ..................... 59
Transition for Entry to Sleep Mode ............................. 62
Transition for Two-Speed Start-up
Transition for Wake from Idle to Run Mode................ 63
Transition for Wake from Sleep (HSPLL) ................... 62
Transition from RC_RUN Mode to
Transition from SEC_RUN Mode to
Transition to RC_RUN Mode...................................... 61
Capture/Compare/PWM Requirements.................... 513
CLKO and I/O Requirements............................ 505, 507
EUSART/AUSART Synchronous Receive
EUSART/AUSART Synchronous Transmission
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Slave Mode Requirements
External Clock Requirements ................................... 503
HLVD Characteristics ............................................... 511
I
2
C Bus Data Requirements (Slave Mode) ............... 519
Timer (OST) and Power-up Timer (PWRT) ...... 509
V
(STRSYNC = 1)................................................ 278
(STRSYNC = 0)................................................ 278
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
Combined Mode ............................................... 207
Combined Mode ............................................... 220
(INTOSC to HSPLL) ......................................... 423
PRI_RUN Mode.................................................. 61
PRI_RUN Mode (HSPLL) ................................... 59
Requirements ................................................... 522
Requirements ................................................... 522
(Master Mode, CKE = 0)................................... 514
(Master Mode, CKE = 1)................................... 515
(Slave Mode, CKE = 0)..................................... 516
(CKE = 1).......................................................... 517
DD
Rise > T
PWRT
DD
)............................................. 77
, V
DD
DD
DD
), Case 1 ....................... 77
), Case 2 ....................... 77
Rise T
DD
DS39960C-page 543
,
PWRT
) ............... 76