PIC18F87K22-I/PTRSL Microchip Technology Inc., PIC18F87K22-I/PTRSL Datasheet - Page 92

• Manufacturer Part Number: PIC18F87K22-I/PTRSL
• Description: 128kB Flash, 4kB RAM, 1kB EE, nanoWatt XLP, GP, 80 TQFP 12x12x1mm TRAY
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F87K22-I/PTRSL

• A/d Inputs: 24-Channel, 12-Bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 69
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 3.8K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 6-8-bit, 5-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F87K22 FAMILY
6.2
6.2.1
The microcontroller clock input, whether from an
internal or external source, is internally divided by four
to generate four non-overlapping quadrature clocks
(Q1, Q2, Q3 and Q4). Internally, the program counter is
incremented on every Q1, with the instruction fetched
from the program memory and latched into the
Instruction Register (IR) during Q4.
The instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow are shown in
FIGURE 6-4:
EXAMPLE 6-3:
DS39960C-page 92
1. MOVLW 55h
2. MOVWF PORTB
3. BRA
4. BSF
5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
OSC2/CLKO
(RC mode)
PIC18 Instruction Cycle
SUB_1
CLOCKING SCHEME
PORTA, BIT3 (Forced NOP)
OSC1
PC
Q1
Q2
Q3
Q4
Q1
CLOCK/INSTRUCTION CYCLE
INSTRUCTION PIPELINE FLOW
Execute INST (PC – 2)
Fetch INST (PC)
Figure
Q2
Fetch 1
T
PC
CY
6-4.
Q3
0
Q4
Execute 1
Fetch 2
T
CY
1
Q1
Fetch INST (PC + 2)
Execute INST (PC)
Q2
Execute 2
Fetch 3
PC + 2
T
CY
2
6.2.2
An “Instruction Cycle” consists of four Q cycles, Q1
through Q4. The instruction fetch and execute are pipe-
lined in such a manner that a fetch takes one instruction
cycle, while the decode and execute take another
instruction cycle. However, due to the pipelining, each
instruction effectively executes in one cycle. If an
instruction (such as GOTO) causes the program counter
to change, two cycles are required to complete the
instruction. (See
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
Q3
Q4
Execute 3
Fetch 4
T
CY
INSTRUCTION FLOW/PIPELINING
3
Q1
Execute INST (PC + 2)
Example
Fetch INST (PC + 4)
Fetch SUB_1 Execute SUB_1
Flush (NOP)
Q2
PC + 4
T
 2011 Microchip Technology Inc.
CY
6-3.)
4
Q3
Q4
T
CY
Internal
Phase
Clock
5