PIC24FJ64GA002-I/SO Microchip Technology Inc., PIC24FJ64GA002-I/SO Datasheet - Page 129

• Manufacturer Part Number: PIC24FJ64GA002-I/SO
• Description: MCU, 16-Bit, 28-Pin, 64KB Flash, 8KB RAM, 21 I/O, Nanowatt
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ64GA002-I/SO

• A/d Inputs: 10 Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/UART
• Memory Capacity: 64 Kbytes
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Inputs: 21
• Number Of Pins: 28
• Package Type: 28-pin SOIC
• Programmable Memory: 64K Bytes
• Ram Size: 8K Bytes
• Speed: 32 MHz
• Timers: 5-16-bit
• Voltage, Range: 2-3.6 V
• Voltage, Rating: 2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

13.0
13.1
When the OCM control bits (OCxCON<2:0>) are set to
‘100’, the selected output compare channel initializes
the OCx pin to the low state and generates a single
output pulse.
To generate a single output pulse, the following steps
are required (these steps assume the timer source is
initially turned off, but this is not a requirement for the
module operation):
1.
2.
3.
4.
5.
6.
7.
8.
9.
© 2007 Microchip Technology Inc.
Note 1: This data sheet summarizes the features of
Determine the instruction clock cycle time. Take
into account the frequency of the external clock
to the timer source (if one is used) and the timer
prescaler settings.
Calculate time to the rising edge of the output
pulse relative to the TMRy start value (0000h).
Calculate the time to the falling edge of the pulse
based on the desired pulse width and the time to
the rising edge of the pulse.
Write the values computed in steps 2 and 3
above into the Output Compare x register,
OCxR, and the Output Compare x Secondary
register, OCxRS, respectively.
Set Timer Period register, PRy, to value equal to
or greater than value in OCxRS, the Output
Compare x Secondary register.
Set the OCM bits to ‘100’ and the OCTSEL
(OCxCON<3>) bit to the desired timer source.
The OCx pin state will now be driven low.
Set the TON (TyCON<15>) bit to ‘1’, which
enables the compare time base to count.
Upon the first match between TMRy and OCxR,
the OCx pin will be driven high.
When the incrementing timer, TMRy, matches the
Output Compare x Secondary register, OCxRS,
the second and trailing edge (high-to-low) of the
pulse is driven onto the OCx pin. No additional
pulses are driven onto the OCx pin and it remains
at low. As a result of the second compare match
event, the OCxIF interrupt flag bit is set, which
will result in an interrupt if it is enabled, by set-
ting the OCxIE bit. For further information on
peripheral interrupts, refer to Section 6.0
“Interrupt Controller”.
2: This peripheral contains input functions
OUTPUT COMPARE
Setup for Single Output Pulse
Generation
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
associated “PIC24F Family Reference
Manual” chapter.
that may need to be configured by the
peripheral pin select feature. For more
information, see Section 9.4 “Peripheral
Pin Select”.
PIC24FJ64GA004 FAMILY
Preliminary
10. To initiate another single pulse output, change the
The output compare module does not have to be dis-
abled after the falling edge of the output pulse. Another
pulse can be initiated by rewriting the value of the
OCxCON register.
13.2
When the OCM control bits (OCxCON<2:0>) are set to
‘101’, the selected output compare channel initializes
the OCx pin to the low state and generates output
pulses on each and every compare match event.
For the user to configure the module for the generation
of a continuous stream of output pulses, the following
steps are required (these steps assume the timer
source is initially turned off, but this is not a requirement
for the module operation):
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. As a result of the second compare match event,
11. When the compare time base and the value in its
12. Steps 8 through 11 are repeated and a continuous
Timer and Compare register settings, if needed,
and then issue a write to set the OCM bits to ‘100’.
Disabling and re-enabling of the timer and clear-
ing the TMRy register are not required, but may
be advantageous for defining a pulse from a
known event time boundary.
Determine the instruction clock cycle time. Take
into account the frequency of the external clock
to the timer source (if one is used) and the timer
prescaler settings.
Calculate time to the rising edge of the output
pulse relative to the TMRy start value (0000h).
Calculate the time to the falling edge of the pulse
based on the desired pulse width and the time to
the rising edge of the pulse.
Write the values computed in step 2 and 3 above
into the Output Compare x register, OCxR, and
the Output Compare x Secondary register,
OCxRS, respectively.
Set Timer Period register, PRy, to value equal to
or greater than value in OCxRS.
Set the OCM bits to ‘101’ and the OCTSEL bit to
the desired timer source. The OCx pin state will
now be driven low.
Enable the compare time base by setting the TON
(TyCON<15>) bit to ‘1’.
Upon the first match between TMRy and OCxR,
the OCx pin will be driven high.
When the compare time base, TMRy, matches the
OCxRS, the second and trailing edge (high-to-low)
of the pulse is driven onto the OCx pin.
the OCxIF interrupt flag bit set.
respective Timer Period register match, the TMRy
register resets to 0x0000 and resumes counting.
stream of pulses is generated indefinitely. The
OCxIF flag is set on each OCxRS/TMRy compare
match event.
Setup for Continuous Output
Pulse Generation
DS39881B-page 127