PIC24FJ64GA002-I/SO Microchip Technology Inc., PIC24FJ64GA002-I/SO Datasheet - Page 190

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PIC24FJ64GA002-I/SO

Manufacturer Part Number
PIC24FJ64GA002-I/SO
Description
MCU, 16-Bit, 28-Pin, 64KB Flash, 8KB RAM, 21 I/O, Nanowatt
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC24FJ64GA002-I/SO

A/d Inputs
10 Channel, 10-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
0 Bytes
Input Output
21
Interface
I2C/SPI/UART
Memory Capacity
64 Kbytes
Memory Type
Flash
Number Of Bits
16
Number Of Inputs
21
Number Of Pins
28
Package Type
28-pin SOIC
Programmable Memory
64K Bytes
Ram Size
8K Bytes
Speed
32 MHz
Timers
5-16-bit
Voltage, Range
2-3.6 V
Voltage, Rating
2-3.6 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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0
PIC24FJ64GA004 FAMILY
REGISTER 20-2:
DS39881B-page 188
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-13
bit 12-11
bit 10
bit 9-8
bit 7
bit 6
bit 5-2
bit 1
bit 0
VCFG2
R/W-0
BUFS
R-0
VCFG2:VCFG0: Voltage Reference Configuration bits
Unimplemented: Read as ‘0’
CSCNA: Scan Input Selections for CH0+ S/H Input for MUX A Input Multiplexer Setting bit
1 = Scan inputs
0 = Do not scan inputs
Unimplemented: Read as ‘0’
BUFS: Buffer Fill Status bit (valid only when BUFM = 1)
1 = A/D is currently filling buffer 08-0F, user should access data in 00-07
0 = A/D is currently filling buffer 00-07, user should access data in 08-0F
Unimplemented: Read as ‘0’
SMPI3:SMPI0: Sample/Convert Sequences Per Interrupt Selection bits
1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence
1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence
.....
0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence
0000 = Interrupts at the completion of conversion for each sample/convert sequence
BUFM: Buffer Mode Select bit
1 = Buffer configured as two 8-word buffers (AD1BUFn<15:8> and AD1BUFn<7:0>)
0 = Buffer configured as one 16-word buffer (AD1BUFn<15:0>)
ALTS: Alternate Input Sample Mode Select bit
1 = Uses MUX A input multiplexer settings for first sample, then alternates between MUX B and
0 = Always uses MUX A input multiplexer settings
VCFG1
R/W-0
VCFG2:VCFG0
MUX A input multiplexer settings for all subsequent samples
U-0
AD1CON2: A/D CONTROL REGISTER 2
000
001
010
011
1xx
W = Writable bit
‘1’ = Bit is set
VCFG0
SMPI3
R/W-0
R/W-0
External V
External V
SMPI2
R/W-0
R/W-0
Preliminary
AV
AV
AV
V
R
DD
DD
DD
+
REF
REF
+ pin
+ pin
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SMPI1
R/W-0
U-0
External V
External V
CSCNA
SMPI0
R/W-0
R/W-0
AV
AV
AV
V
R
SS
SS
SS
-
REF
REF
© 2007 Microchip Technology Inc.
- pin
- pin
x = Bit is unknown
R/W-0
BUFM
U-0
R/W-0
ALTS
U-0
bit 8
bit 0

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