PIC24FJ64GA002-I/SO Microchip Technology Inc., PIC24FJ64GA002-I/SO Datasheet - Page 147

• Manufacturer Part Number: PIC24FJ64GA002-I/SO
• Description: MCU, 16-Bit, 28-Pin, 64KB Flash, 8KB RAM, 21 I/O, Nanowatt
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ64GA002-I/SO

• A/d Inputs: 10 Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/UART
• Memory Capacity: 64 Kbytes
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Inputs: 21
• Number Of Pins: 28
• Package Type: 28-pin SOIC
• Programmable Memory: 64K Bytes
• Ram Size: 8K Bytes
• Speed: 32 MHz
• Timers: 5-16-bit
• Voltage, Range: 2-3.6 V
• Voltage, Rating: 2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

15.2
To compute the Baud Rate Generator reload value, use
Equation 15-1.
EQUATION 15-1:
15.3
The I2CxMSK register (Register 15-3) designates
address bit positions as “don’t care” for both 7-Bit and
10-Bit Addressing modes. Setting a particular bit loca-
tion (= 1) in the I2CxMSK register causes the slave
TABLE 15-1:
© 2007 Microchip Technology Inc.
Legend: Shaded rows represent invalid reload values for a given F
Note 1:
Note 1: Based on T
Note:
2:
3:
4:
Required
100 kHz
100 kHz
100 kHz
400 kHz
400 kHz
400 kHz
400 kHz
System
Setting Baud Rate When
Operating as a Bus Master
Slave Address Masking
1 MHz
1 MHz
1 MHz
F
PLL are disabled.
SCL
Based on T
This is the closest value to 400 kHz for this value of F
F
I2CxBRG cannot have a value of less than 2.
To comply with I
acknowledged by the I
CY
or
F
I2CxBRG
= 2 MHz is the minimum input clock frequency to have F
SCL
I
2
C™ CLOCK RATES
=
COMPUTING BAUD RATE
RELOAD VALUE
CY
--------------------------------------------- -
2
CY
⋅
=
= T
(
= T
I2CxBRG
⎛
⎝
2
CY
------------------ -
2 F
C™ definition, the addresses in Table 15-2 on page 146 are reserved and will not be
F
CY
⋅
F
CY
/2, Doze mode and PLL are disabled.
CY
16 MHz
16 MHz
16 MHz
/2; Doze mode and
8 MHz
4 MHz
8 MHz
4 MHz
2 MHz
8 MHz
4 MHz
SCL
2
F
C peripheral operating in Slave mode.
CY
⎞
⎠
+
–
1
)
1
(1)
(1)
PIC24FJ64GA004 FAMILY
Preliminary
(Decimal)
79
39
19
19
9
4
2
7
3
1
I2CxBRG Value
module to respond whether the corresponding address
bit value is a ‘0’ or a ‘1’. For example, when I2CxMSK
is set to ‘00100000’, the slave module will detect both
addresses, ‘0000000’ and ‘00100000’.
To enable address masking, the IPMI (Intelligent
Peripheral Management Interface) must be disabled by
clearing the IPMIEN bit (I2CxCON<11>).
15.3.1
The I2C1 has limited peripheral pin select capability.
The SDA1/SCL1 pins have alternative multiplexing
based on the setting of the I2C1SEL bit. The default
pins are used when the bit is set.
CY
Note:
.
SCL
(Hexadecimal)
SCL
and F
PERIPHERAL PIN SELECT
LIMITATIONS
The I2C1SEL bit is a Configuration bit in
the Flash Configuration Word. It is not part
of the regular device Configuration regis-
ters.
Section 3.1.3
Words”.
= 1 MHz.
4F
27
13
13
9
4
2
7
3
1
CY
.
For
more
“Flash
333 kHz
information,
1 MHz
1 MHz
DS39881B-page 145
100 kHz
100 kHz
100 kHz
400 kHz
400 kHz
400 kHz
Actual
1 MHz
F
Configuration
SCL
(3)
(4)
(2)
see