PIC24FJ64GA002-I/SO Microchip Technology Inc., PIC24FJ64GA002-I/SO Datasheet - Page 164

• Manufacturer Part Number: PIC24FJ64GA002-I/SO
• Description: MCU, 16-Bit, 28-Pin, 64KB Flash, 8KB RAM, 21 I/O, Nanowatt
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ64GA002-I/SO

• A/d Inputs: 10 Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/UART
• Memory Capacity: 64 Kbytes
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Inputs: 21
• Number Of Pins: 28
• Package Type: 28-pin SOIC
• Programmable Memory: 64K Bytes
• Ram Size: 8K Bytes
• Speed: 32 MHz
• Timers: 5-16-bit
• Voltage, Range: 2-3.6 V
• Voltage, Rating: 2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC24FJ64GA004 FAMILY
REGISTER 17-1:
DS39881B-page 162
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-11
bit 10
bit 9
bit 8
bit 7-6
bit 5
bit 4
bit 3
Note 1:
PMPEN
R/W-0
R/W-0
CSF1
2:
Devices with 28 pins do not have PMA<10:2>.
These bits have no effect when their corresponding pins are used as address lines.
PMPEN: Parallel Master Port Enable bit
1 = PMP enabled
0 = PMP disabled, no off-chip access performed
Unimplemented: Read as ‘0’
PSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
ADRMUX1:ADRMUX0: Address/Data Multiplexing Selection bits
11 = Reserved
10 = All 16 bits of address are multiplexed on PMD<7:0> pins
01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper 3 bits are multiplexed on
00 = Address and data appear on separate pins
PTBEEN: Byte Enable Port Enable bit (16-Bit Master mode)
1 = PMBE port enabled
0 = PMBE port disabled
PTWREN: Write Enable Strobe Port Enable bit
1 = PMWR/PMENB port enabled
0 = PMWR/PMENB port disabled
PTRDEN: Read/Write Strobe Port Enable bit
1 = PMRD/PMWR port enabled
0 = PMRD/PMWR port disabled
CSF1:CSF0: Chip Select Function bits
11 = Reserved
10 = PMCS1 functions as chip set
01 = Reserved
00 = Reserved
ALP: Address Latch Polarity bit
1 = Active-high (PMALL and PMALH)
0 = Active-low (PMALL and PMALH)
Unimplemented: Read as ‘0’
CS1P: Chip Select 1 Polarity bit
1 = Active-high (PMCS1/PMCS1)
0 = Active-low (PMCS1/PMCS1)
R/W-0
CSF0
U-0
—
PMCON: PARALLEL PORT CONTROL REGISTER
PMA<10:8>
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
PSIDL
ALP
(1)
ADRMUX1
(2)
(2)
R/W-0
U-0
Preliminary
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
ADRMUX0
R/W-0
R/W-0
CS1P
(1)
PTBEEN
R/W-0
R/W-0
BEP
(1)
© 2007 Microchip Technology Inc.
x = Bit is unknown
PTWREN
WRSP
R/W-0
R/W-0
PTRDEN
R/W-0
R/W-0
RDSP
bit 8
bit 0