PIC16F737-I/SP Microchip Technology Inc., PIC16F737-I/SP Datasheet
PIC16F737-I/SP
Specifications of PIC16F737-I/SP
Related parts for PIC16F737-I/SP
PIC16F737-I/SP Summary of contents
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... Microcontrollers with 10-Bit A/D 2004 Microchip Technology Inc. 28/40/44-Pin, 8-Bit CMOS Flash and nanoWatt Technology PIC16F7X7 Data Sheet DS30498C ...
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... Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. , microID, MPLAB, PIC, PICmicro, PICSTART, ® 8-bit MCUs ® code hopping EE OQ 2004 Microchip Technology Inc. ...
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... Dual Analog Comparators • Programmable Low-Current Brown-out Reset (BOR) Circuitry and Programmable Low-Voltage Detect (LVD) Program Data Memory Device SRAM (# Single-Word (Bytes) Instructions) PIC16F737 4096 368 PIC16F747 4096 368 PIC16F767 8192 368 PIC16F777 8192 368 2004 Microchip Technology Inc. ...
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... DS30498C-page 2 28 RB7/PGD 27 RB6/PGC 26 RB5/AN13/CCP3 25 RB4/AN11 (1) RB3/CCP2 /AN9 24 23 RB2/AN8 22 RB1/AN10 21 RB0/INT/AN12 RC7/RX/DT RC6/TX/CK 17 RC5/SDO 16 RC4/SDI/SDA 15 QFN (28-pin RA2/AN2/V -/CV REF REF 1 RA3/AN3 REF RA4/T0CKI/C1OUT 3 PIC16F737 RA5/AN4/LVDIN/SS/C2OUT 4 PIC16F767 OSC1/CLKI/RA7 6 OSC2/CLKO/RA6 OSC2/CLKO/RA6 32 OSC1/CLKI/RA7 RE2/CS/AN7 RE1/WR/AN6 26 RE0/RD/AN5 25 RA5/AN4/LVDIN/SS/C2OUT 24 23 RA4/T0CKI/C1OUT (1) 21 RB3/CCP2 /AN9 20 RB2/AN8 19 RB1/AN10 ...
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... RD1/PSP1 TQFP (44-pin) RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 RB0/INT/AN12 RB1/AN10 RB2/AN8 (1) RB3/CCP2 /AN9 Note 1: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1. 2004 Microchip Technology Inc. /RE3 1 40 RB7/PGD 2 39 RB6/PGC 3 38 RB5/AN13/CCP3 4 37 RB4/AN11 REF + RB3/CCP2 REF ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS30498C-page 4 2004 Microchip Technology Inc. ...
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... PIC16F747/777 devices are available in 40-pin and 44-pin packages. All devices in the PIC16F7X7 family share common architecture with the following differences: • The PIC16F737 and PIC16F767 have one-half of the total on-chip memory of the PIC16F747 and PIC16F777. • The 28-pin devices have 3 I/O ports, while the 40/44-pin devices have 5. • ...
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... PIC16F7X7 FIGURE 1-1: PIC16F737 AND PIC16F767 BLOCK DIAGRAM 13 Standard Flash Program Memory 4K/ Program 14 Bus Instruction Register Direct Addr 8 Instruction Decode & Start-up Timer Control Timing Generation OSC1/CLKI OSC2/CLKO V DD Timer0 Timer1 Comparators CCP1 Note 1: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1. ...
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... Decode & Control Timing Generation OSC1/CLKI OSC2/CLKO V DD Timer0 Timer1 Comparators CCP1 Note 1: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1. 2004 Microchip Technology Inc. 8 Data Bus Program Counter RAM 8-Level Stack File (13-bit) Registers 368 x 8 (1) RAM Addr 9 ...
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... PIC16F7X7 TABLE 1-2: PIC16F737 AND PIC16F767 PINOUT DESCRIPTION PDIP SOIC QFN Pin Name SSOP Pin # Pin # OSC1/CLKI/RA7 9 6 OSC1 CLKI RA7 OSC2/CLKO/RA6 10 7 OSC2 CLKO RA6 MCLR/V /RE3 MCLR V PP RE3 RA0/AN0 2 27 RA0 AN0 RA1/AN1 3 28 RA1 AN1 RA2/AN2/V -/ REF ...
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... TABLE 1-2: PIC16F737 AND PIC16F767 PINOUT DESCRIPTION (CONTINUED) PDIP SOIC QFN Pin Name SSOP Pin # Pin # RB0/INT/AN12 21 18 RB0 INT AN12 RB1/AN10 22 19 RB1 AN10 RB2/AN8 23 20 RB2 AN8 RB3/CCP2/AN9 24 21 RB3 (4) CCP2 AN9 RB4/AN11 25 22 RB4 AN11 RB5/AN13/CCP3 26 23 RB5 ...
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... PIC16F7X7 TABLE 1-2: PIC16F737 AND PIC16F767 PINOUT DESCRIPTION (CONTINUED) PDIP SOIC QFN Pin Name SSOP Pin # Pin # RC0/T1OSO/T1CKI 11 8 RC0 T1OSO T1CKI RC1/T1OSI/CCP2 12 9 RC1 T1OSI (4) CCP2 RC2/CCP1 13 10 RC2 CCP1 RC3/SCK/SCL 14 11 RC3 SCK SCL RC4/SDI/SDA 15 12 RC4 SDI SDA ...
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... Slave Port mode (for interfacing to a microprocessor bus). 4: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise. 5: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1. 2004 Microchip Technology Inc. TQFP I/O/P Buffer Pin # ...
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... CCP3 capture input, compare output, PWM output. (2) 16 TTL/ST I/O Digital I/O. I/O In-Circuit Debugger and ICSP™ programming clock. (2) 17 TTL/ST I/O Digital I/O. I/O In-Circuit Debugger and ICSP programming data. I/O = input/output ST = Schmitt Trigger input Description P = power 2004 Microchip Technology Inc. ...
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... Slave Port mode (for interfacing to a microprocessor bus). 4: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise. 5: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1. 2004 Microchip Technology Inc. TQFP I/O/P Buffer Pin # ...
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... Ground reference for logic and I/O pins. — P — Analog positive supply — Positive supply for logic and I/O pins. — — These pins are not internally connected. These pins 33, 34 should be left unconnected. I/O = input/output ST = Schmitt Trigger input Description P = power 2004 Microchip Technology Inc. ...
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... The PIC16F767/777 devices have 8K words of Flash program memory and the PIC16F737/747 devices have 4K words. The program memory maps for PIC16F7X7 devices are shown in Figure 2-1. Accessing a location above the physically implemented address will cause a wraparound. ...
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... PIC16F7X7 FIGURE 2-2: DATA MEMORY MAP FOR PIC16F737 AND THE PIC16F767 File Address (*) Indirect addr. Indirect addr. 00h OPTION_REG TMR0 01h PCL 02h 03h STATUS 04h FSR PORTA 05h 06h PORTB 07h PORTC 08h PORTE 09h 0Ah PCLATH 0Bh INTCON PIR1 ...
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... CCP2CON 1Eh ADRESH 1Fh ADCON0 20h General Purpose Register 96 Bytes 7Fh Bank 0 Unimplemented data memory locations read as ‘0’. * Not a physical register. 2004 Microchip Technology Inc. File Address (*) Indirect addr. 80h TMR0 81h PCL PCL 82h STATUS STATUS 83h FSR ...
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... CCP1M1 CCP1M0 --00 0000 88, 180 OERR RX9D 0000 000x 134, 180 0000 0000 139, 180 0000 0000 141, 180 92, 180 xxxx xxxx 92, 180 xxxx xxxx CCP2M1 CCP2M0 --00 0000 88, 180 xxxx xxxx 160, 180 CHS3 ADON 0000 0000 152, 180 2004 Microchip Technology Inc. ...
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... This bit always reads as a ‘1’. 7: OSCCON<OSTS> bit resets to ‘0’ with dual-speed start-up and LP HS-PLL selected as the oscillator. 8: RE3 is an input only. The state of the TRISE3 bit has no effect and will always read ‘1’. 2004 Microchip Technology Inc. Bit 5 Bit 4 ...
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... DC C 21, 180 0001 1xxx 30, 180 xxxx xxxx — — 64, 181 1111 1111 — — — — — — 23, 180 ---0 0000 INT0IF RBIF 25, 180 0000 000x — RD 32, 181 1--- ---0 — — — — — — 2004 Microchip Technology Inc. ...
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... Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the Status register as 000u u1uu (where u = unchanged). ...
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... R/W-1 R/W-1 T0CS T0SE PSA TMR0 Rate WDT Rate 128 1 : 128 1 : 256 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-1 R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown 2004 Microchip Technology Inc. ...
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... At least one of the RB7:RB4 pins changed state (must be cleared in software None of the RB7:RB4 pins have changed state Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON< ...
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... Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. R/W-0 R/W-0 R/W-0 R/W-0 RCIE TXIE SSPIE CCP1IE ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown 2004 Microchip Technology Inc. ...
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... TMR1 register did not overflow Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Inter- rupt Enable bit, GIE (INTCON<7>). User software should ensure the appropriate inter- rupt bits are clear prior to enabling an interrupt ...
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... DS30498C-page 26 R/W-0 U-0 R/W-0 U-0 LVDIE — BCLIE W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared 2004 Microchip Technology Inc. R/W-0 R/W-0 — CCP3IE CCP2IE bit Master mode 2 C Master mode x = Bit is unknown ...
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... No TMR1 register compare match occurred PWM mode: Unused. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>). ...
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... Configuration Word register). U-0 U-0 U-0 U-0 — — — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-1 R/W-0 R/W-1 SBOREN POR BOR bit Bit is unknown 2004 Microchip Technology Inc. ...
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... RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. 2004 Microchip Technology Inc. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push ...
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... FFh 17Fh 1FFh Bank 1 Bank 2 Bank 3 INDIRECT ADDRESSING 0x20 ;initialize pointer FSR ;to RAM INDF ;clear INDF register FSR, F ;inc pointer FSR, 4 ;all done? NEXT ;no clear next ;yes continue Indirect Addressing 7 FSR Register 0 Location Select 2004 Microchip Technology Inc. ...
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... Initiates a Flash read cleared in hardware. The RD bit can only be set (not cleared) in software Flash read completed Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. When interfacing to the program memory block, the PMDATH:PMDATA registers form a two-byte word which holds PMADRH:PMADR registers form a two-byte word which holds the 13-bit address of the Flash location being accessed ...
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... EEPROM Address Register High Byte ---- xxxx ---u uuuu EEPROM Data Register High Byte — — — — — Value on Value on: Bit 0 all other POR, BOR Resets xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu --xx xxxx --uu uuuu RD 1--- ---0 1--- ---0 2004 Microchip Technology Inc. ...
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... AT S strip cut crystals varies with the crystal chosen (typically F between 2004 Microchip Technology Inc. TABLE 4-1: Osc Type Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation. These values were not optimized ...
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... PORTA (RA6). Figure 4-3 shows the pin connections for the ECIO Oscillator mode. To Internal FIGURE 4-3: Logic Clock from Ext. System OSC2 for which the EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) OSC1/CLKI PIC16F7X7 I/O (OSC2) RA6 2004 Microchip Technology Inc. ...
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... Recommended values 100 k EXT C > EXT 2004 Microchip Technology Inc. 4.5 Internal Oscillator Block The PIC16F7X7 devices include an internal oscillator block which generates two different clock signals; either can be used as the system’s clock source. This ) values and the can eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins ...
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... U-0 R/W-0 R/W-0 R/W-0 — TUN5 TUN4 TUN3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared 8 clock cycles (approximately R/W-0 R/W-0 R/W-0 TUN2 TUN1 TUN0 bit Bit is unknown 2004 Microchip Technology Inc. ...
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... The system clock select bits, SCS1:SCS0, select the clock source that is used when the device is operating in power-managed modes. When the bits are cleared (SCS<1:0> = 00), the system clock source comes from 2004 Microchip Technology Inc. PIC16F7X7 the main oscillator ...
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... R/W-0 R/W-0 R-0 R-0 (1) IRCF1 IRCF0 OSTS IOFS ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared 2004 Microchip Technology Inc. R/W-0 R/W-0 SCS1 SCS0 bit Bit is unknown ...
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... Time sensitive code should wait for the IOFS bit in the OSCCON register to become set before continuing. This bit can be monitored to ensure that the frequency is stable before using the system clock in time critical applications. 2004 Microchip Technology Inc. LP, XT, HS, RC Timer1 OSCCON<6:4> 8 MHz ...
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... Following a wake-up from Sleep mode or POR, CPU start-up is invoked to allow the CPU to become ready for code execution. Following a change from INTRC, the OST count of 1024 cycles must occur. Refer to Section 4.6.4 “Modifying the IRCF Bits” for further details. 2004 Microchip Technology Inc. ...
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... T . DLY INP 2004 Microchip Technology Inc. If the system clock does not come from the INTRC (31.25 kHz) when the SCS bits are changed and the IRCF bits in the OSCCON register are configured for a frequency other than INTRC, the frequency may not be stable immediately. The IOFS bit (OSCCON< ...
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... Original SCS<1:0> clock switching event will occur if the final state of the SCS bits is different from the original SCS ( Modified Final SCS<1:0> SCS<1:0> 00 – no change 01 10 – INTRC 11 10 – no change 11 00 – Oscillator 01 defined by FOSC<2:0> 2004 Microchip Technology Inc. ...
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... If the primary system clock is either RC or EC, an internal delay timer (5-10 s) will suspend operation after exiting Secondary Clock mode to allow the CPU to become ready for code execution. 2004 Microchip Technology Inc. PIC16F7X7 4.7.3.1 Returning to Primary Clock Source Sequence Changing back to the primary oscillator from SEC_RUN or RC_RUN can be accomplished by either changing SCS< ...
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... SCS<1:0> SCS<1:0> OSTS OSTS Program Program Counter Counter Note 30. typical. INP minimum. OSC SCS INP DLY INP Refer to parameter D032 in Section 18.0 “Electrical Characteristics”. DS30498C-page 44 P (1) P (1) INP (2) INP ( SCS (4) SCS ( (3) ( OSC OSC (5) ( DLY DLY 2004 Microchip Technology Inc. ...
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... EPU 4: Refer to parameter D032 in Section 18.0 “Electrical Characteristics”. 2004 Microchip Technology Inc. no oscillator start-up time required because the primary clock is already stable; however, there is a delay between the wake-up event and the following Q2. An internal delay timer of 5-10 s will suspend operation after the Reset to allow the CPU to become ready for code execution ...
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... PIC16F7X7 FIGURE 4-11: TIMING LP CLOCK TO PRIMARY SYSTEM CLOCK AFTER RESET (EC, RC, INTRC T1OSI OSC1 OSC2 CPU (2) T CPU Start-up System Clock MCLR OSTS Program PC Counter Note 30. 5-10 s. CPU DS30498C-page 0001h 0000h 0002h 0003h 0004h 2004 Microchip Technology Inc. ...
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... LP, XT, HS 1024 Clocks 00 (Due to Reset) LP, XT, HS Note 1: If the new clock source is the INTOSC or INTOSC postscaler, then the IOFS bit will be set 4 ms (approx.) after the clock change. 2004 Microchip Technology Inc. OSTS IOFS T1RUN System bit bit bit Clock ...
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... If the primary oscillator is XT HS, the core will continue to run off T1OSC and execute the SLEEP command. When Sleep is exited, the part will resume operation with the primary oscillator after the OST has expired. 2004 Microchip Technology Inc. ...
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... Section 15.1 “Configuration Bits” for details). When they are not used as port pins, RA6 and RA7 and their associated TRIS and LAT bits are read as ‘0’. 2004 Microchip Technology Inc. The other PORTA pins are multiplexed with analog inputs, the analog V comparator voltage reference output ...
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... WR DD PORTA P Data Latch D WR I/O pin N TRISA TRIS Latch SS TTL D RD PORTA To Comparator To A/D Module Channel Input To A/D Module V BLOCK DIAGRAM OF RA3/AN3/V + PIN REF I/O pin Analog Input Mode TTL Input Buffer RD TRISA Input REF 2004 Microchip Technology Inc. ...
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... BLOCK DIAGRAM OF RA4/T0CKI/C1OUT PIN Data Comparator Mode = 011, 101, 001 Bus D Q Comparator 1 Output WR PORTA CK Q Data Latch TRISA CK Q TRIS Latch RD TRISA RD PORTA TMR0 Clock Input 2004 Microchip Technology Inc. -/CV PIN REF REF REF 1 0 Analog Input Mode Q PIC16F7X7 RA2/AN2/V -/ REF N ...
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... Data Bus D Q Comparator 2 Output WR PORTA CK Q Data Latch TRISA CK Q TRIS Latch RD TRISA RD PORTA SS Input LVDIN To A/D Module Channel Input DS30498C-page 52 Comparator Mode = 011, 101 1 0 Analog Input Mode RA5/AN4/LVDIN/ N SS/C2OUT pin V SS TTL Buffer 2004 Microchip Technology Inc. ...
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... Data Bus PORTA Q CK Data Latch TRISA CK Q TRIS Latch RD TRISA RD PORTA (F = 1x1) OSC EMUL + F = 00x, 010 OSC Note 1: CLKO signal is 1/4 of the F 2004 Microchip Technology Inc. = 1x1) From OSC1 Oscillator Circuit 1x1) OSC EMUL EMUL + F = 00x,010 OSC (F = 1x0,011) OSC frequency ...
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... BLOCK DIAGRAM OF OSC1/CLKI/RA7 PIN Data Bus PORTA CK Q Data Latch TRISA TRIS Latch RD TRISA Q RD PORTA (F = 10x) EMUL OSC DS30498C-page 54 Oscillator Circuit ( 10x) EMUL OSC 011) OSC OSC1/CLKI = 10x) OSC NEMUL TTL Buffer 1 0 RA7 pin (F = 10x) OSC 2004 Microchip Technology Inc. ...
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... Shaded cells are not used by PORTA. Note: When using the SSP module in SPI Slave mode and SS enabled, the A/D converter must be set to one of the following modes, where PCFG2:PCFG0 = 100, 101, 11x. 2004 Microchip Technology Inc. Buffer TTL Input/output or analog input. ...
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... Since the TRIS bit override is in effect while the peripheral is enabled, read-modify- write instructions (BSF, BCF, XORWF) with TRISB as destination should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. 2004 Microchip Technology Inc. ...
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... BLOCK DIAGRAM OF RB1/AN10 PIN Analog (1) RBPU Input Mode Data Bus WR PORTB WR TRISB To A/D Channel Input Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 2004 Microchip Technology Inc. Data Latch TRIS Latch Input Mode ...
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... Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. DS30498C-page 58 Data Latch TRIS Latch D Q Analog CK Input Mode Input Buffer RD TRISB Q RD PORTB V DD Weak P Pull-up I/O pin TTL PORTB 2004 Microchip Technology Inc. ...
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... To CCP Module Input Note 1: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 3: The SDA Schmitt Trigger conforms to the I 2004 Microchip Technology Inc. (1) /AN9 PIN Analog ...
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... Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. DS30498C-page 60 Analog Input Mode (1) RBPU Q Q Analog Input Mode Input Buffer Q Analog Input Mode Weak P Pull- I/O pin TTL Latch PORTB EN Q3 2004 Microchip Technology Inc. ...
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... WR PORTB WR TRISB RD PORTB Set RBIF From other RB7:RB4 pins To CCP Module Input To A/D Channel Input Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 2004 Microchip Technology Inc. Analog Input Mode 1 0 Data Latch ...
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... Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. DS30498C-page 62 Data Latch TRIS Latch TRISB Q RD PORTB Program Mode/ICD Q Schmitt Trigger Buffer V DD Weak P Pull-up I/O pin TTL Input Buffer Latch PORTB EN Q3 2004 Microchip Technology Inc. ...
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... Port/Program Mode/ICD PGD (1) RBPU Data Bus WR PORTB WR TRISB PGD DRVEN Set RBIF From other RB7:RB4 pins Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 2004 Microchip Technology Inc Data Latch TRIS Latch TRISB ...
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... T0SE PSA PS2 PS1 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000 Value on Value on: Bit 0 all other POR, BOR Resets RB0 xx00 0000 uu00 0000 1111 1111 1111 1111 PS0 1111 1111 1111 1111 2004 Microchip Technology Inc. ...
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... Peripheral Input Note 1: I/O pins have diode protection Port/Peripheral Select signal selects between port data and peripheral output. 3: Peripheral OE (Output Enable) is only activated if Peripheral Select is active. 2004 Microchip Technology Inc. FIGURE 5-17: Port/Peripheral Select Peripheral Data Out Data Bus D WR ...
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... Input/output port pin or AUSART asynchronous receive or synchronous data. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RC5 RC4 RC3 RC2 RC1 2 C mode). Value on Value on: Bit 0 all other POR, BOR Resets RC0 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 2004 Microchip Technology Inc. ...
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... PORTD and TRISD Registers This section is not applicable to the PIC16F737 or PIC16F767. PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configureable as an input or output. PORTD can be configured as an 8-bit wide micro- processor port (Parallel Slave Port) by setting control bit, PSPMODE (TRISE< ...
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... PIC16F7X7 5.5 PORTE and TRISE Register This section is not applicable to the PIC16F737 or PIC16F767. PORTE has four pins, RE0/RD/AN5, RE1/WR/AN6, RE2/CS/AN7 and MCLR/V /RE3, which are individu- PP ally configureable as inputs or outputs. These pins have Schmitt Trigger input buffers. RE3 is only available as an input if MCLRE is ‘ ...
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... TRISE1: Direction Control bit for pin RE1/WR/AN6 1 = Input 0 = Output bit 0 TRISE0: Direction Control bit for pin RE0/RD/AN5 1 = Input 0 = Output Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. R-0 R/W-0 R/W-0 OBF IBOV PSPMODE ( Writable bit U = Unimplemented bit, read as ‘0’ ...
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... PIC16F7X7 5.6 Parallel Slave Port The Parallel Slave Port (PSP) is not implemented on the PIC16F737 or PIC16F767. PORTD operates as an 8-bit wide Parallel Slave Port or microprocessor port when control bit, PSPMODE (TRISE<4>), is set. In Slave mode asynchronously readable and writable by an external system using the ...
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... Shaded cells are not used by the Parallel Slave Port. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F737/767; always maintain these bits clear. 2: RE3 is an input only. The state of the TRISE3 bit has no effect and will always read ‘1’. ...
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... PIC16F7X7 NOTES: DS30498C-page 72 2004 Microchip Technology Inc. ...
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... Prescaler WDT Enable bit Note: T0CS, T0SE, PSA and PS2:PS0 are (OPTION_REG<5:0>). 2004 Microchip Technology Inc. Counter mode is selected by setting bit, T0CS (OPTION_REG<5>). In Counter mode, Timer0 will increment, either on every rising or falling edge of pin RA4/T0CKI/C1OUT. determined by the Timer0 Source Edge Select bit, T0SE (OPTION_REG< ...
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... WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. The prescaler is not readable or writable. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count but will not change the prescaler assignment. 2004 Microchip Technology Inc. ...
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... Bit Value TMR0 Rate WDT Rate 000 001 010 011 100 101 1 : 128 110 1 : 256 111 Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. R/W-1 R/W-1 R/W-1 R/W-1 T0CS T0SE PSA (1) ® Mid-Range MCU Family Reference Manual” (DS33023) must 128 W = Writable bit U = Unimplemented bit, read as ‘ ...
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... Bit 3 Bit 2 PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x T0CS T0SE PSA PS2 Value on Value on Bit 1 Bit 0 all other POR, BOR Resets xxxx xxxx uuuu uuuu 0000 000u PS1 PS0 1111 1111 1111 1111 2004 Microchip Technology Inc. ...
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... Timer1 oscillator or another source. Timer1 can also be used to provide Real-Time Clock (RTC) functionality to applications with only a minimal addition of external components and code overhead. 2004 Microchip Technology Inc. PIC16F7X7 7.1 Timer1 Operation Timer1 can operate in one of three modes: • ...
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... R = Readable bit -n = Value at POR DS30498C-page 78 R/W-0 R/W-0 R/W-0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC /4) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 TMR1CS TMR1ON bit Bit is unknown 2004 Microchip Technology Inc. ...
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... TMR1H T1OSC T1OSO/T1CKI T1OSI Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain. 2004 Microchip Technology Inc. 7.4 Timer1 Operation in Synchronized Counter Mode Counter mode is selected by setting bit TMR1CS. In this mode, the timer increments on every rising edge of ...
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... This may produce an unpredictable value in the Timer register. Reading the 16-bit value requires some care. The example codes provided in Example 7-1 Example 7-2 demonstrate how to write to and read Timer1 while it is running in Asynchronous mode. 2004 Microchip Technology Inc. and ...
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... Capacitor values are for design guidance only. 2004 Microchip Technology Inc. 7.7 Timer1 Oscillator Layout Considerations The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity ...
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... Asynchronous operation, external oscillator ; Initialize timekeeping registers ; Enable Timer1 interrupt ; Preload for 1 sec overflow ; Clear interrupt flag ; Increment seconds ; 60 seconds elapsed? ; No, done ; Clear seconds ; Increment minutes ; 60 seconds elapsed? ; No, done ; Clear minutes ; Increment hours ; 24 hours elapsed? ; No, done ; Clear hours ; Done 2004 Microchip Technology Inc. ...
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... T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 -uuu uuuu Legend unknown unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F737/767 devices; always maintain these bits clear. 2004 Microchip Technology Inc. Bit 5 Bit 4 ...
Page 86
... PIC16F7X7 NOTES: DS30498C-page 84 2004 Microchip Technology Inc. ...
Page 87
... Additional information on timer modules is available in ® the “PICmicro Mid-Range MCU Family Reference Manual” (DS33023). 2004 Microchip Technology Inc. 8.1 Timer2 Prescaler and Postscaler The prescaler and postscaler counters are cleared when any of the following occurs: • a write to the TMR2 register • ...
Page 88
... PR2 Timer2 Period Register Legend unknown unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F737/767 devices; always maintain these bits clear. DS30498C-page 86 R/W-0 R/W-0 R/W Writable bit U = Unimplemented bit, read as ‘ ...
Page 89
... PWM Capture None. PWM Compare None. 2004 Microchip Technology Inc. 9.2 CCP2 Module Capture/Compare/PWM Register 2 (CCPR2) is com- prised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. The special event trigger is gen- erated by a compare match ...
Page 90
... R = Readable bit -n = Value at POR DS30498C-page 88 U-0 R/W-0 R/W-0 R/W-0 — CCPxX CCPxY CCPxM3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 CCPxM2 CCPxM1 CCPxM0 bit Bit is unknown 2004 Microchip Technology Inc. ...
Page 91
... The user should keep bit, CCP1IE (PIE1<2>), clear to avoid false interrupts and should clear the flag bit, CCP1IF, following any such change in operating mode. 2004 Microchip Technology Inc. 9.4.4 CCP PRESCALER There are four prescaler settings specified by bits, CCP1M3:CCP1M0 ...
Page 92
... Legend unknown unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1. Note 1: The PSP is not implemented on the PIC16F737/767 devices; always maintain these bits clear. DS30498C-page 90 9.5.4 SPECIAL EVENT TRIGGER In this mode, an internal hardware trigger is generated which may be used to initiate an action ...
Page 93
... Reset Reset Period Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2 2004 Microchip Technology Inc. 9.6.1 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula: EQUATION 9-1: PWM Period = [(PR2 • 4 • T PWM frequency is defined as 1/[PWM period] ...
Page 94
... Legend unknown unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F737/767 devices; always maintain these bits clear. DS30498C-page 92 9.6.3 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1 ...
Page 95
... Additionally, a fourth pin may be used when in a Slave mode of operation: • Slave Select (SS) – RA5/AN4/LVDIN/SS/C2OUT Figure 10-1 shows the block diagram of the MSSP module when operating in SPI mode. 2004 Microchip Technology Inc. PIC16F7X7 FIGURE 10-1: MSSP BLOCK DIAGRAM (SPI™ MODE) ...
Page 96
... During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. R-0 R-0 R-0 CKE D Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R-0 R-0 R-0 R bit Bit is unknown 2004 Microchip Technology Inc. ...
Page 97
... SPI Master mode, clock = F 0000 = SPI Master mode, clock = F Note: Bit combinations not specifically listed here are either reserved or implemented mode only. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 SSPM2 /64 ...
Page 98
... Example 10-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP Status register (SSPSTAT) indicates the various status conditions. 2004 Microchip Technology Inc. ...
Page 99
... Shift Register (SSPSR) MSb LSb PROCESSOR 1 2004 Microchip Technology Inc. 10.3.4 TYPICAL CONNECTION Figure 10-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their pro- grammed clock edge and latched on the opposite edge of the clock ...
Page 100
... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit 2 bit 5 bit 4 bit 3 bit 1 bit 2 bit 5 bit 4 bit 3 bit Clock Modes bit 0 bit 0 bit 0 bit 0 Next Q4 Cycle after Q2 2004 Microchip Technology Inc. ...
Page 101
... Interrupt Flag SSPSR to SSPBUF 2004 Microchip Technology Inc. must be high. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output ...
Page 102
... SDI (SMP = 0) bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS30498C-page 100 bit 6 bit 2 bit 5 bit 4 bit 3 bit 6 bit 5 bit 4 bit 2 bit 3 bit 1 bit 0 bit 0 Next Q4 Cycle after Q2 bit 1 bit 0 bit 0 Next Q4 Cycle after Q2 2004 Microchip Technology Inc. ...
Page 103
... Shaded cells are not used by the MSSP in SPI™ mode. Note 1: The PSPIF and PSPIE bits are reserved on 28-pin devices; always maintain these bits clear. 2004 Microchip Technology Inc. 10.3.10 BUS MODE COMPATIBILITY ...
Page 104
... SSPIF interrupt is set. Addr Match During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. Set, Reset S, P bits (SSPSTAT Reg operation mode operation. The 2 C Slave mode. When the 2004 Microchip Technology Inc. ...
Page 105
... Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc MODE) REGISTER (ADDRESS 94h) R-0 R-0 ...
Page 106
... R/W-0 SSPEN CKP SSPM3 SSPM2 2 /(4 * (SSPADD + 1)) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 SSPM1 SSPM0 bit 0 C conditions were not valid for x = Bit is unknown 2004 Microchip Technology Inc. ...
Page 107
... For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc MODE) REGISTER 2 (ADDRESS 91h) R/W-0 R/W-0 R/W-0 ...
Page 108
... An ACK pulse is generated. 4. MSSP Interrupt Flag bit, SSPIF (PIR1<3>), is set (interrupt is generated if enabled) on the falling edge of the ninth SCL pulse Slave 2 C pins using a Read-Modify-Write 2 C mode may stop 2 C communication may 2 C pins) using the 2 C communication 2004 Microchip Technology Inc. ...
Page 109
... When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set or bit SSPOV (SSPCON<6>) is set. 2004 Microchip Technology Inc. PIC16F7X7 An MSSP interrupt is generated for each data transfer byte. Flag bit, SSPIF (PIR1<3>), must be cleared in software ...
Page 110
... PIC16F7X7 2 FIGURE 10-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) DS30498C-page 108 2004 Microchip Technology Inc. ...
Page 111
... FIGURE 10-9: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) 2004 Microchip Technology Inc. PIC16F7X7 DS30498C-page 109 ...
Page 112
... PIC16F7X7 2 FIGURE 10-10: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) DS30498C-page 110 2004 Microchip Technology Inc. ...
Page 113
... FIGURE 10-11: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) 2004 Microchip Technology Inc. PIC16F7X7 DS30498C-page 111 ...
Page 114
... R/W bit set to ‘1’. After the third address sequence is performed, the UA bit is not set, the module is now configured in Transmit mode and clock stretching is controlled by the BF flag as in 7-bit Slave Transmit mode (see Figure 10-11). 2004 Microchip Technology Inc. ...
Page 115
... CKP bit will not violate the minimum high time requirement for SCL (see Figure 10-12). FIGURE 10-12: CLOCK SYNCHRONIZATION TIMING SDA SCL CKP Write SSPCON 2004 Microchip Technology Inc. DX Master device asserts clock Master device deasserts clock PIC16F7X7 DX – 1 DS30498C-page 113 ...
Page 116
... PIC16F7X7 2 FIGURE 10-13: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) DS30498C-page 114 2004 Microchip Technology Inc. ...
Page 117
... FIGURE 10-14: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS) 2004 Microchip Technology Inc. PIC16F7X7 DS30498C-page 115 ...
Page 118
... UA bit will not is enabled be set and the slave will begin receiving data after the Acknowledge (Figure 10-15). Address is compared to general call address after ACK, set interrupt R ACK Cleared in software SSPBUF is read Receiving Data ACK ‘0’ ‘1’ 2004 Microchip Technology Inc. ...
Page 119
... Generate a Stop condition on SDA and SCL. FIGURE 10-16: MSSP BLOCK DIAGRAM (I SDA SDA In SCL SCL In Bus Collision 2004 Microchip Technology Inc. Note: The MSSP module, when configured Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a Start condition and ...
Page 120
... SSPCON2 register (SSPCON2<6>). 10. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 11. The user generates a Stop condition by setting the Stop enable bit, PEN (SSPCON2<2>). 12. Interrupt is generated once the Stop condition is complete. 2004 Microchip Technology Inc. ...
Page 121
... C™ interface does not conform to the 400 kHz I 100 kHz) in all details, but may be used with care where higher rates are required by the application. 2004 Microchip Technology Inc. Once the given operation is complete (i.e., transmis- sion of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state ...
Page 122
... SCL BRG 03h Value BRG Reload DS30498C-page 120 DX – 1 BRG decrements on Q2 and Q4 cycles 02h 01h 00h (hold off) SCL is sampled high, reload takes place and BRG starts its count SCL allowed to transition high 03h 02h 2004 Microchip Technology Inc. ...
Page 123
... FIGURE 10-19: FIRST START BIT TIMING Write to SEN bit occurs here SDA SCL 2004 Microchip Technology Inc. 10.4.8.1 WCOL Status Flag If the user writes the SSPBUF when a Start sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). ...
Page 124
... SSPCON2 is disabled until the Repeated Start condition is complete. Set S (SSPSTAT<3>) SDA = 1, At completion of Start bit, SCL = 1 hardware clears RSEN bit and sets SSPIF BRG BRG BRG 1st bit Write to SSPBUF occurs here T BRG Sr = Repeated Start T BRG 2004 Microchip Technology Inc. ...
Page 125
... SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). WCOL must be cleared in software. 2004 Microchip Technology Inc. 10.4.10.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is ...
Page 126
... PIC16F7X7 2 FIGURE 10-21: I C™ MASTER MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS) DS30498C-page 124 2004 Microchip Technology Inc. ...
Page 127
... FIGURE 10-22: I C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) 2004 Microchip Technology Inc. PIC16F7X7 DS30498C-page 125 ...
Page 128
... SDA sampled high. P bit (SSPSTAT<4>) is set. PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set T BRG BRG BRG BRG SCL brought high after T BRG SDA asserted low before rising edge of clock to setup Stop condition Cleared in software BRG 2004 Microchip Technology Inc. ...
Page 129
... BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA SCL BCLIF 2004 Microchip Technology Inc. 10.4.17 MULTI-MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitra- tion. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a ‘ ...
Page 130
... Repeated Start or Stop conditions. SEN cleared automatically because of bus collision. SSP module resets into Idle state. SSPIF and BCLIF are cleared in software SSPIF and BCLIF are cleared in software 2004 Microchip Technology Inc. ...
Page 131
... BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION Less than T SDA pulled low by other master. SDA Reset BRG and assert SDA. SCL SEN BCLIF S SSPIF 2004 Microchip Technology Inc. SDA = 0, SCL = BRG BRG SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SDA = 0, SCL = 1 Set S ...
Page 132
... Repeated Start condition is complete. Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. Cleared in software T T BRG BRG 2004 Microchip Technology Inc. ‘0’ ‘0’ Interrupt cleared in software ‘0’ ...
Page 133
... SCL PEN BCLIF P SSPIF 2004 Microchip Technology Inc. The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD<6:0> and counts down to 0. After the BRG times out, SDA is sampled ...
Page 134
... PIC16F7X7 NOTES: DS30498C-page 132 2004 Microchip Technology Inc. ...
Page 135
... TSR full bit 0 TX9D: 9th bit of Transmit Data, can be Parity bit Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. The AUSART can be configured in the following modes: • Asynchronous (full-duplex) • Synchronous – Master (half-duplex) • Synchronous – Slave (half-duplex) Bit SPEN (RCSTA< ...
Page 136
... R = Readable bit -n = Value at POR DS30498C-page 134 R/W-0 R/W-0 R/W-0 RX9 SREN CREN ADDEN W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R-0 R-0 R-x FERR OERR RX9D bit Bit is unknown 2004 Microchip Technology Inc. ...
Page 137
... SPBRG Baud Rate Generator Register Legend unknown, — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG. 2004 Microchip Technology Inc. It may be advantageous to use the high baud rate (BRGH = 1) even for slower baud clocks. This is because the F baud rate error in some cases. ...
Page 138
... MHz OSC SPBRG % Kbaud Value Error (decimal) — — — — — — 2.441 1.71 255 9.615 0.16 64 19.531 1.72 31 28.409 1.36 21 32.895 2.10 18 56.818 1.36 10 2.441 — 255 625.000 — 0 2004 Microchip Technology Inc. ...
Page 139
... Microchip Technology Inc MHz MHz OSC OSC SPBRG % % Value Kbaud Error Error (decimal) 0 207 0.300 0 +0.16 51 1.202 +0.16 +0. ...
Page 140
... TSR register (if the TSR is empty). In such a case, an incorrect ninth data bit may be loaded in the TSR register. Data Bus TXREG Register 8 LSb Pin Buffer 0 and Control TSR Register TRMT TX9 TX9D RC6/TX/CK pin SPEN 2004 Microchip Technology Inc. ...
Page 141
... Shaded cells are not used for asynchronous transmission. Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear. 2004 Microchip Technology Inc. 5. Enable the transmission by setting bit TXEN which will also set bit TXIF. ...
Page 142
... RX9 Recovery RX9D RCREG Register RCIF Interrupt RCIE Start bit 7/8 Stop bit 7/8 Stop bit bit 0 bit bit Word 2 Word 1 RCREG RCREG FERR LSb 1 0 Start FIFO 8 Data Bus Start Stop bit bit 7/8 bit 2004 Microchip Technology Inc. ...
Page 143
... Shaded cells are not used for asynchronous reception. Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear. 2004 Microchip Technology Inc. 6. Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE is set ...
Page 144
... CPU. OERR CREN 64 RSR Register MSb or 16 Stop (8) 7 Data RX9 Recovery Enable Load of Receive Buffer RX9D RCREG Register RCIF Interrupt RCIE FERR LSb 1 0 Start 8 8 FIFO 8 Data Bus 2004 Microchip Technology Inc. ...
Page 145
... Baud Rate Generator Register Legend unknown, — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear. 2004 Microchip Technology Inc. Start Stop bit 8 bit ...
Page 146
... Enable the transmission by setting bit TXEN 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 7. Start transmission by loading data to the TXREG register using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set. 2004 Microchip Technology Inc. ...
Page 147
... Note: Sync Master mode, SPBRG = 0. Continuous transmission of two 8-bit words. FIGURE 11-10: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT pin RC6/TX/CK pin Write to TXREG Reg TXIF bit TRMT bit TXEN bit 2004 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 TMR0IE INT0IE RBIE TMR0IF INT0IF ...
Page 148
... TRMT Value on Value on: Bit 0 all other POR, BOR Resets RBIF 0000 000x 0000 000u 0000 0000 RX9D 0000 000x 0000 000x 0000 0000 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 2004 Microchip Technology Inc. ...
Page 149
... RC6/TX/CK pin Write to bit SREN SREN bit ‘0’ CREN bit RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0. 2004 Microchip Technology Inc bit 1 bit 2 bit 3 bit 4 bit 5 PIC16F7X7 bit 6 bit 7 ‘ ...
Page 150
... TXEN SYNC — BRGH TRMT Value on Value on: Bit 0 all other POR, BOR Resets RBIF 0000 000x 0000 000u RX9D 0000 000x 0000 000x 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 2004 Microchip Technology Inc. ...
Page 151
... Shaded cells are not used for synchronous slave reception. Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices, always maintain these bits clear. 2004 Microchip Technology Inc. When setting up a Synchronous Slave Reception, follow these steps: 1 ...
Page 152
... PIC16F7X7 NOTES: DS30498C-page 150 2004 Microchip Technology Inc. ...
Page 153
... ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The Analog-to-Digital (A/D) Converter module has 11 inputs for the PIC16F737 and PIC16F767 devices and 14 for the PIC16F747 AND PIC16F777 devices. The A/D converter allows conversion of an analog input signal to a corresponding 10-bit digital number. A new feature for the A/D converter is the addition of programmable acquisition time ...
Page 154
... Channel 10 (AN10) 1011 = Channel 11 (AN11) 1100 = Channel 12 (AN12) 1101 = Channel 13 (AN13) 111x = Unused Note 1: Selecting AN5 through AN7 on the 28-pin product variant (PIC16F737 and PIC16F767) will result in a full-scale conversion as unimplemented channels are connected to V bit 2 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress ...
Page 155
... D 1110 D 1111 Legend Analog input Digital I/O Note: AN5 through AN7 are only available on the 40-pin product variant (PIC16F747 and PIC16F777). Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 VCFG1 VCFG0 PCFG3 SS - (RA2) REF DD + (RA3) REF ...
Page 156
... GO/DONE bit (ADCON0 register) is cleared and A/D Interrupt Flag bit, ADIF, is set. The block diagram of the A/D module is shown in Figure 12-1. U-0 U-0 U-0 — — — bit 0 is added before the A Bit is unknown 2004 Microchip Technology Inc. ...
Page 157
... FIGURE 12-1: A/D BLOCK DIAGRAM A/D Converter (Reference Voltage) (Reference Voltage) 2004 Microchip Technology Inc. 2. Configure A/D interrupt (if desired): • Clear ADIF bit • Set ADIE bit • Set PEIE bit • Set GIE bit 3. Wait the required acquisition time (if required). ...
Page 158
... HOLD delay must complete before acquisition can begin again Sampling Switch LEAKAGE V = 0.6V T ±500 the minimum acquisition time, , see ACQ ® Mid-Range MCU Family Reference SS C HOLD = DAC Capacitance = 120 Sampling Switch (k ) 2004 Microchip Technology Inc. ...
Page 159
... When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only recommended for Sleep operation. 3: For extended voltage devices (LF), please refer to Section 18.0 “Electrical Characteristics”. 2004 Microchip Technology Inc. 12.3 Selecting the A/D Conversion Clock The A/D conversion time per bit is defined as T A/D conversion requires a minimum 12 T conversion ...
Page 160
... Analog levels on any pin that is defined as a digital input, but not as an analog input, may cause the digital input buffer to consume current that is out of the device’s specification 2004 Microchip Technology Inc. ...
Page 161
... Time (Holding capacitor is disconnected) Set GO/DONE bit (Holding capacitor continues acquiring input) 2004 Microchip Technology Inc. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register pair will NOT be updated with the partially completed A/D ...
Page 162
... OBF Legend unknown unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F737/767 devices; always maintain these bits clear. 2: These registers are reserved on the PIC16F737/767 devices. 3: RE3 is an input only. The state of the TRISE3 bit has no effect and will always read ‘1’. ...
Page 163
... CM2:CM0: Comparator Mode bits Figure 13-1 shows the Comparator modes and CM2:CM0 bit settings. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. The CMCON register (Register 13-1) controls the comparator input and output multiplexers. A block diagram of the various comparator configurations is are shown in Figure 13-1 ...
Page 164
... REF (Read as ‘0’ Digital Input CIS (CMCON<3>) is the Comparator Input Switch Off C1 (Read as ‘0’ Off ‘ ’ C2 (Read C1OUT C2OUT C1OUT C2OUT CIS = CIS = 1 C1OUT CIS = 0 IN CIS = 1 C2OUT REF From Comparator V Module REF 2004 Microchip Technology Inc. ...
Page 165
... V and V and can be applied to either SS DD pin of the comparator(s). 2004 Microchip Technology Inc. 13.3.2 INTERNAL REFERENCE SIGNAL The comparator module also allows the selection of an internally generated voltage reference for the compar- ators. Section 14.0 “Comparator Voltage Reference + is less IN Module” ...
Page 166
... Any read or write of CMCON will end the mismatch condition. b) Clear flag bit CMIF. A mismatch condition will continue to set flag bit CMIF. Reading CMCON will end the mismatch condition and allow flag bit CMIF to be cleared. - CxINV 2004 Microchip Technology Inc. ...
Page 167
... TRISA PORTA Data Direction Register Legend unknown unchanged, — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module. 2004 Microchip Technology Inc. 13.9 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 13-4. Since the analog pins are connected to a ...
Page 168
... PIC16F7X7 NOTES: DS30498C-page 166 2004 Microchip Technology Inc. ...
Page 169
... When CVRR = 1/4 (CV REF Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. supply voltage (also referred directly from V voltage at the top of the ladder is CV where V is the saturation voltage of the power SAT switch transistor. This reference will only be as ...
Page 170
... Bit 3 Bit 2 Bit 1 CVRR — CVR3 CVR2 CVR1 C2INV C1INV CIS CM2 CM1 R 8R CVRR CVR3 CVR2 CVR1 CVR0 Value on Value on Bit 0 all other POR Resets CVR0 000- 0000 000- 0000 CM0 0000 0111 0000 0111 2004 Microchip Technology Inc. ...
Page 171
... Reset while the power supply stabilizes and is enabled or disabled using a configuration bit. With these two timers on-chip, most applications need no external Reset circuitry. 2004 Microchip Technology Inc. PIC16F7X7 Sleep mode is designed to offer a very low-current power-down mode. The user can wake-up from Sleep through external Reset, Watchdog Timer wake-up or through an interrupt ...
Page 172
... CP: Flash Program Memory Code Protection bits 1 = Code protection off 0 = 0000h to 1FFFh code-protected for PIC16F767/777 and 0000h to 0FFFh for PIC16F737/747 (all protected) bit 12 CCPMX: CCP2 Multiplex bit 1 = CCP2 is on RC1 0 = CCP2 is on RB3 bit 11 DEBUG: In-Circuit Debugger Mode bit ...
Page 173
... Internal External Switchover mode enabled 0 = Internal External Switchover mode disabled bit 0 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. U-1 U-1 R/P-1 U-1 U-1 — — BORSEN — ...
Page 174
... This delay runs in parallel with any other timers. See Table 15-4 for a full description of Reset states of all registers. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 15- Enable PWRT Enable OST 2004 Microchip Technology Inc. Chip_Reset Q ...
Page 175
... If these conditions are not met, the device must be held in Reset until the operating conditions are met. For more information, see Application Note AN607 “Power-up Trouble Shooting” (DS00607). 2004 Microchip Technology Inc. 15.5 Power-up Timer (PWRT) The Power-up Timer (PWRT) of the PIC16F7X7 is a counter that uses the INTRC oscillator as the clock input ...
Page 176
... LVDIF bit. This voltage is software programmable to any one of 16 values (see Figure 15-4). The trip point is selected by programming the LVDL3:LVDL0 bits (LVDCON<3:0>). , A Legend Time is the B . The difference, T – the total LVD trip point = Minimum valid device operating voltage 2004 Microchip Technology Inc. ...
Page 177
... FIGURE 15-5: LOW-VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM V DD LVDIN Externally Generated Trip Point 2004 Microchip Technology Inc. LVDIN LVD Control Register Internally Generated Reference Voltage 1.2V pin, LVDIN (Figure 15-5). This gives users flexibility ...
Page 178
... Value at POR DS30498C-page 176 U-0 R-0 R/W-0 R/W-0 — IRVST LVDEN LVDL3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-1 R/W-0 R/W-1 LVDL2 LVDL1 LVDL0 bit Bit is unknown 2004 Microchip Technology Inc. ...
Page 179
... Internally Generated Reference Stable CASE LVDIF Enable LVD Internally Generated Reference Stable 2004 Microchip Technology Inc. PIC16F7X7 The following steps are needed to set up the LVD module: 1. Write the value to the LVDL3:LVDL0 bits (LVDCON register) which selects the desired LVD trip point. 2. ...
Page 180
... BOR cleared, indicating a Brown-out Reset occurred. When the Brown-out Reset is disabled, the state of the BOR bit is unpredictable. Bit 1 is Power-on Reset Status bit, POR cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset. 2004 Microchip Technology Inc. ...
Page 181
... Interrupt Wake-up from Sleep Legend unchanged unknown, — = unimplemented bit, read as ‘0’ Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 2004 Microchip Technology Inc. Brown-out Reset PWRTE = 1 PWRTE = 0 1024 • 1024 • ...
Page 182
... PCL STATUS 0001 1xxx FSR xxxx xxxx PORTA xx0x 0000 PORTB xx00 0000 PORTC xxxx xxxx PORTD xxxx xxxx PORTE (PIC16F737/767) ---- x--- PORTE (PIC16F747/777) ---- x000 PCLATH ---0 0000 INTCON 0000 000x PIR1 0000 0000 PIR2 000- 0-00 TMR1L xxxx xxxx TMR1H ...
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... INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Register Brown-out Reset TRISA 1111 1111 TRISB 1111 1111 TRISC 1111 1111 TRISD 1111 1111 TRISE (PIC16F737/767) ---- 1--- TRISE (PIC16F747/777) 0000 1111 PIE1 0000 0000 PIE2 000- 0-00 PCON ---- -1qq OSCCON -000 1000 OSCTUNE ...
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... Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 15-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED NETWORK): CASE MCLR Internal POR PWRT Time-out OST Time-out Internal Reset DS30498C-page 182 T PWRT T OST T PWRT T OST T PWRT T OST 2004 Microchip Technology Inc. THROUGH DD THROUGH DD THROUGH DD ...
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... FIGURE 15-10: SLOW RISE TIME (MCLR TIED MCLR Internal POR PWRT Time-out OST Time-out Internal Reset 2004 Microchip Technology Inc. THROUGH RC NETWORK PWRT T OST PIC16F7X7 DS30498C-page 183 ...
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... Q cycle. The latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set regardless of the status of their corresponding mask bit, PEIE bit or the GIE bit. Wake-up (If in Sleep mode) TMR0IF TMR0IE INT0IF INT0IE RBIF RBIE PEIE GIE 2004 Microchip Technology Inc. Interrupt to CPU ...
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... SWAPF W_TEMP, F ;Swap W_TEMP SWAPF W_TEMP, W ;Swap W_TEMP into W 2004 Microchip Technology Inc. 15.15.3 PORTB INTCON CHANGE An input change on PORTB<7:4> sets flag bit, RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit, RBIE (INTCON<4>), see Section 2.2 “Data Memory Organization”. ...
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... The PSA and PS<2:0> bits (OPTION_REG) have the same function as in previous versions of the PIC16 family of microcontrollers. From TMR0 Clock Source 0 1 PSA WDTPS<3:0> Prescaler Cleared Cleared at end of OST Postscaler 8 PS<2:0> To TMR0 0 1 PSA WDT Time-out Postscaler (PSA = 1) Cleared Cleared at end of OST 2004 Microchip Technology Inc. ...
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... WDTCON — — Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 15-1 for operation of these bits. 2004 Microchip Technology Inc. U-0 R/W-0 R/W-1 — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN W = Writable bit U = Unimplemented bit, read as ‘0’ ...
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... System clock is switched to primary source (LP HS). The software may read the OSTS bit to determine when the switchover takes place so that any software timing edges can be adjusted 0001h 0000h Two-Speed Start-up Sequence begin execution by INTRC 0003h 0004h 0005h 2004 Microchip Technology Inc. ...
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... The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 2004 Microchip Technology Inc. The FSCM sample clock is generated by dividing the INTRC clock by 64. This will allow enough time between FSCM sample clocks for a system clock edge to occur ...
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... SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execu- tion of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. ). IHMC wake-up (if WDT was 2 C). 2004 Microchip Technology Inc. ...
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... GIE = 1 assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line. 4: CLKO is not available in these oscillator modes but shown here for timing reference. 2004 Microchip Technology Inc. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes ...
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... Guide” (DS30277). FIGURE 15-17 GND, External PP DD Connector Signals + CLK Data I/O not been * Isolation devices (as required). microcontrollers can be serially TYPICAL IN-CIRCUIT SERIAL PROGRAMMING™ CONNECTION To Normal Connections * PIC16F7X7 MCLR/V /RE3 PP RB6 RB7 * * * Normal Connections 2004 Microchip Technology Inc. ...
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... A read operation is performed on a register even if the instruction writes to that register. 2004 Microchip Technology Inc. For example, a “CLRF PORTB” instruction will read PORTB, clear all the data bits, then write the result back to PORTB. This example would have the ...
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... TO, PD 0000 0110 0100 1kkk kkkk kkkk Z 1000 kkkk kkkk 00xx kkkk kkkk 0000 0000 1001 01xx kkkk kkkk 0000 0000 1000 TO, PD 0000 0110 0011 C, DC, Z 110x kkkk kkkk Z 1010 kkkk kkkk ® Mid-Range MCU 2004 Microchip Technology Inc. ...
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... Status Affected: Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. 2004 Microchip Technology Inc. BCF k Syntax: Operands: Operation: Status Affected: ...
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... Decrement f [ label ] DECF f 127 d [0,1] (f) – 1 (destination) Z Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. 2004 Microchip Technology Inc. ...
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... Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. 2004 Microchip Technology Inc. PIC16F7X7 INCFSZ Increment f, Skip if 0 Syntax: [ label ] INCFSZ f,d ...
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... GIE None Return with Literal label ] RETLW 255 k (W); TOS PC None The W register is loaded with the eight-bit literal ‘k’. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. 2004 Microchip Technology Inc. ...