PIC16F737-I/SP Microchip Technology Inc., PIC16F737-I/SP Datasheet - Page 158

• Manufacturer Part Number: PIC16F737-I/SP
• Description: 28 PIN, 7 KB FLASH, 368 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F737-I/SP

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 192 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F7X7
12.1
For the A/D converter to meet its specified accuracy, the
charge holding capacitor (C
fully charge to the input channel voltage level. The
analog input model is shown in Figure 12-2. The source
impedance (R
impedance directly affect the time required to charge the
capacitor C
varies over the device voltage (V
The maximum recommended impedance for analog
sources is 2.5 k . As the impedance is decreased, the
acquisition time may be decreased. After the analog
input channel is selected (changed), this acquisition
must be done before the conversion can be started.
EQUATION 12-1:
FIGURE 12-2:
DS30498C-page 156
T
T
T
ACQ
C
ACQ
Note 1: The reference voltage (V
2: The charge holding capacitor (C
3: The maximum recommended impedance for analog sources is 10 k . This is required to meet the pin
4: After a conversion has completed, a 2.0 T
A/D Acquisition Requirements
=
=
=
=
=
=
=
=
HOLD
leakage specification.
During this time, the holding capacitor is not connected to the selected A/D input channel.
Legend: C
Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
T
2 s + T
C
-120 pF (1 k + 7 k + 10 k ) In(0.0004885)
16.47 s
2 s + 16.47 s + [(50°C – 25 C)(0.05 s/ C)
19.72 s
S
AMP
HOLD
) and the internal sampling switch (R
. The sampling switch (R
+ T
(R
C
VA
V
I
R
SS
C
C
ACQUISITION TIME
+ [(Temperature – 25°C)(0.05 s/°C)]
ANALOG INPUT MODEL
LEAKAGE
IC
PIN
T
IC
HOLD
+ T
R
+ R
S
COFF
HOLD
SS
ANx
C
5 pF
+ R
PIN
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to
= Interconnect Resistance
= Sampling Switch
= Sample/Hold Capacitance (from DAC)
) must be allowed to
DD
various junctions
S
) In(1/2047)
), see Figure 12-2.
REF
SS
) has no effect on the equation since it cancels itself out.
) impedance
HOLD
V
DD
V
V
) is not discharged after each conversion.
T
T
SS
= 0.6V
= 0.6V
)
AD
delay must complete before acquisition can begin again.
I
±500 nA
LEAKAGE
To
Equation 12-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
To calculate the minimum acquisition time, T
the “PICmicro
Manual” (DS33023).
R
IC
calculate
1K
V
Sampling
SS R
DD
Switch
6V
5V
4V
3V
2V
®
SS
Mid-Range MCU Family Reference
the
Sampling Switch
5 6 7 8 9 10 11
V
minimum
SS
 2004 Microchip Technology Inc.
C
= DAC Capacitance
= 120 pF
(k )
HOLD
acquisition
ACQ
, see
time,