PIC16F737-I/SP Microchip Technology Inc., PIC16F737-I/SP Datasheet - Page 128

• Manufacturer Part Number: PIC16F737-I/SP
• Description: 28 PIN, 7 KB FLASH, 368 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F737-I/SP

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 192 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F7X7
10.4.12
An Acknowledge sequence is enabled by setting the
Acknowledge
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (T
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for T
pulled low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 10-23).
10.4.12.1
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 10-23:
FIGURE 10-24:
DS30498C-page 126
ACKNOWLEDGE SEQUENCE
TIMING
WCOL Status Flag
Note: T
SCL
SDA
Note: T
SSPIF
Sequence
Acknowledge sequence starts here,
SDA
SCL
Falling edge of
9th clock
Write to SSPCON2,
BRG
BRG
ACKNOWLEDGE SEQUENCE WAVEFORM
STOP CONDITION RECEIVE OR TRANSMIT MODE
Set SSPIF at the end
of receive
ACK
= one Baud Rate Generator period.
= one Baud Rate Generator period.
ACKEN = 1, ACKDT = 0
BRG
set PEN
Enable
. The SCL pin is then
write to SSPCON2
bit,
8
T
T
D0
BRG
BRG
SDA asserted low before rising edge of clock to setup Stop condition
ACKEN
BRG
T
SCL brought high after T
BRG
Cleared in
software
)
T
BRG
P
SCL = 1 for T
after SDA sampled high. P bit (SSPSTAT<4>) is set.
ACK
T
BRG
10.4.13
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2<2>). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is
sampled low, the Baud Rate Generator is reloaded and
counts down to ‘0’. When the Baud Rate Generator
times out, the SCL pin will be brought high and one
T
SDA pin will be deasserted. When the SDA pin is sam-
pled high while SCL is high, the P bit (SSPSTAT<4>) is
set. A T
bit is set (Figure 10-24).
10.4.13.1
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
BRG
T
Set SSPIF at the end
of Acknowledge sequence
BRG
9
PEN bit (SSPCON2<2>) is cleared by
(Baud Rate Generator rollover count) later, the
hardware and the SSPIF bit is set
BRG
BRG
BRG
, followed by SDA = 1 for T
STOP CONDITION TIMING
later, the PEN bit is cleared and the SSPIF
ACKEN automatically cleared
WCOL Status Flag
Cleared in
software
 2004 Microchip Technology Inc.
BRG